Planar transistors with wrap-around gates and wrap-around source and drain contacts

ABSTRACT

Disclosed herein are IC structures, packages, and devices that include planar III-N transistors with wrap-around gates and/or one or more wrap-around source/drain (S/D) contacts. An example IC structure includes a support structure (e.g., a substrate) and a planar III-N transistor. The transistor includes a channel stack of a III-N semiconductor material and a polarization material, provided over the support structure, a pair of S/D regions provided in the channel stack, and a gate stack of a gate dielectric material and a gate electrode material provided over a portion of the channel stack between the S/D regions, where the gate stack at least partially wraps around an upper portion of the channel stack.

BACKGROUND

Solid-state devices that can be used in high frequency and/or high voltage applications are of great importance in modern semiconductor technologies. For example, radio frequency (RF) integrated circuits (RFIC) and power management integrated circuits (PMIC) may be critical functional blocks in system on a chip (SoC) implementations. Such SoC implementations may be found in mobile computing platforms such as smartphones, tablets, laptops, netbooks, and the like. In such implementations, the RFIC and PMIC and RFIC are important factors for power efficiency and form factor, and can be equally or even more important than logic and memory circuits.

Due, in part, to their large band gap and high mobility, III-N material based transistors, such as gallium nitride (GaN) based transistors, may be particularly advantageous for high frequency and high voltage applications.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments will be readily understood by the following detailed description in conjunction with the accompanying drawings. To facilitate this description, like reference numerals designate like structural elements. Embodiments are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings.

FIGS. 1A-1C provide various cross-sectional side views illustrating an integrated circuit (IC) structure that includes a planar III-N transistor with a wrap-around gate and wrap-around source/drain (S/D) contacts, according to some embodiments of the present disclosure.

FIGS. 2A-2C provide various cross-sectional side views illustrating an IC structure that includes a planar III-N transistor with a wrap-around gate, wrap-around S/D contacts, and a buffer layer, according to some embodiments of the present disclosure.

FIG. 3 is a flow diagram of an example method of manufacturing an IC structure that includes a planar III-N transistor with a wrap-around gate and/or wrap-around S/D contacts, in accordance with various embodiments of the present disclosure.

FIGS. 4A-4E are various views illustrating different example stages in the manufacture of an IC structure using the method of FIG. 3, according to some embodiments of the present disclosure.

FIGS. 5A-5B are top views of a wafer and dies that include one or more IC structures having one or more planar III-N transistors with wrap-around gates and/or one or more wrap-around S/D contacts in accordance with any of the embodiments of the present disclosure.

FIG. 6 is a cross-sectional side view of an IC package that may include one or more IC structures having one or more planar III-N transistors with wrap-around gates and/or one or more wrap-around S/D contacts in accordance with any of the embodiments of the present disclosure.

FIG. 7 is a cross-sectional side view of an IC device assembly that may include one or more IC structures having one or more planar III-N transistors with wrap-around gates and/or one or more wrap-around S/D contacts in accordance with any of the embodiments of the present disclosure.

FIG. 8 is a block diagram of an example computing device that may include one or more IC structures having one or more planar III-N transistors with wrap-around gates and/or one or more wrap-around S/D contacts in accordance with any of the embodiments of the present disclosure.

FIG. 9 is a block diagram of an example RF device that may include one or more IC structures having one or more planar III-N transistors with wrap-around gates and/or one or more wrap-around S/D contacts in accordance with any of the embodiments of the present disclosure.

DETAILED DESCRIPTION

Overview

As mentioned above, III-N material based transistors have properties that make them particularly advantageous for certain applications. For example, because GaN has a larger band gap (about 3.4 electronvolts (eV)) than silicon (Si; band gap of about 1.1 eV), a GaN transistor is expected to withstand a larger electric field (resulting, e.g., from applying a large voltage to the drain, Vdd) before suffering breakdown, compared to a Si transistor of similar dimensions. Furthermore, GaN transistors may advantageously employ a 2D electron gas (2 DEG) (i.e., a group of electrons, an electron gas, free to move in two dimensions but tightly confined in the third dimension, e.g., a 2D sheet charge) as its transport channel, enabling high mobilities without using impurity dopants. For example, the 2D sheet charge may be formed at an abrupt heterojunction interface formed by deposition (e.g., epitaxial deposition), on GaN, of a charge-inducing film of a material having larger spontaneous and piezoelectric polarization, compared to GaN (such a film is generally referred to as a “polarization layer”). Providing a polarization layer on a III-N material such as GaN allows forming very high charge densities without intentionally added impurity dopants, which, in turn, enables high mobilities.

Despite the advantages, there are some challenges associated with III-N transistors which hinder their large-scale implementation.

One such challenge resides in gate control of III-N transistors. For achieving the required performance, the gate length of III-N transistors is being aggressively scaled (reduced). As a result, short channel effects (SCE) come into play, significantly degrading transistor performance. The issue may be particularly severe for enhancement mode devices which require gate voltage to be positive at all times. SCE cause drain induced barrier lowering (DIBL), which may cause the threshold voltage of the transistor to become negative at sufficiently high drain biases, leading to leakage currents at zero gate voltages.

Another challenge associated with III-N transistors resides in contact resistance between S/D contacts (i.e., S/D electrode material) and S/D regions (e.g., the highly doped regions in the channel material of a transistor). Since parasitic effects are ever so important for short channel transistors, any improvements to contact resistance are always desirable.

Disclosed herein are IC structures, packages, and device assemblies that include planar III-N transistors with wrap-around gates and/or one or more wrap-around S/D contacts. An example IC structure includes a support structure/material, which may be, e.g., a substrate, a die, or a chip, and further includes a planar III-N transistor. The III-N transistor includes a channel stack of a III-N semiconductor material and a polarization material, provided over the support structure, a pair of S/D regions provided in the channel stack, and a gate stack of a gate dielectric material and a gate electrode material provided over a portion of the channel stack between the S/D regions, where the gate stack at least partially wraps around an upper portion of the channel stack. Providing a gate stack that at least partially wraps around the channel stack allows increasing the contact area between the gate stack and the channel region of the channel stack (i.e., the region in the III-N semiconductor material of the channel stack where a conductive channel forms during the operation of the III-N transistor), which may advantageously improve gate control at the edges of the planar III-N transistor. Providing a wrap-around gate (i.e., a gate stack that at least partially wraps around an upper portion of a channel stack of a transistor) for a planar transistor may enable required performance without having to resort to complex integration schemes associated with non-planar transistors. Further, since a wrap-around gate may be similar to a three-dimensional gate used with non-planar transistors such FinFETs (Fin-based Field Effect Transistors) but on a planar transistor, it may enable taking advantage of the full periphery of the III-N channel stack (which may be shaped as an island) to conduct current and control short channel losses at the edge of the channel stack. Providing a wrap-around S/D contact material as one or both contacts to the S/D regions (e.g., S/D contact material that at least partially wraps around an upper portion of one or both of the S/D regions of a transistor) for a planar transistor allows increasing the contact area between the S/D contacts and the S/D regions, which may advantageously result in improved contact resistance.

While there may be advantages in implementing both, the wrap-around gate and both of the wrap-around S/D contacts in a given planar III-N transistor, in various embodiments, a planar III-N transistor may implement 1) the wrap-around gate as described herein but not the wrap-around S/D contacts, 2) one or more of the wrap-around S/D contacts as described herein but not the wrap-around gate, or 3) the wrap-around gate as described herein and the wrap-around S/D contact as described herein but only for one of the S/D regions.

As used herein, the term “III-N semiconductor material” (in the following, also referred to simply as an “III-N material”) refers to a compound semiconductor material with a first sub-lattice of at least one element from group III of the periodic table (e.g., Al, Ga, In) and a second sub-lattice of nitrogen (N). As used herein, the term “III-N transistor” refers to a device that includes a III-N material (which may include one or more different III-N materials, e.g., a plurality of different III-N materials stacked over one another) as an active material in which a conductive channel is formed during operation of the transistor.

While various embodiments described herein may refer to the two-dimensional charge carrier layers as “2 DEG” layers, embodiments described herein are also applicable to systems and material combinations in which 2D hole gas (2 DHG) may be formed, instead of 2 DEG. Thus, unless stated otherwise, embodiments referring to 2 DEG are equally applicable to implementing 2 DHG instead, all of such embodiments being within the scope of the present disclosure. Furthermore, while various embodiments described herein refer to planar III-N transistors, they are equally applicable to transistors that use semiconductor materials other than III-N materials as active materials.

Each of the structures, packages, methods, devices, and systems of the present disclosure may have several innovative aspects, no single one of which being solely responsible for the all of the desirable attributes disclosed herein. Details of one or more implementations of the subject matter described in this specification are set forth in the description below and the accompanying drawings.

In the following detailed description, various aspects of the illustrative implementations may be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. For example, the term “connected” means a direct electrical or magnetic connection between the things that are connected, without any intermediary devices, while the term “coupled” means either a direct electrical or magnetic connection between the things that are connected, or an indirect connection through one or more passive or active intermediary devices. The term “circuit” means one or more passive and/or active components that are arranged to cooperate with one another to provide a desired function. If used, the terms “oxide,” “carbide,” “nitride,” etc. refer to compounds containing, respectively, oxygen, carbon, nitrogen, etc. Similarly, the terms naming various compounds refer to materials having any combination of the individual elements within a compound (e.g., “gallium nitride” or “GaN” refers to a material that includes gallium and nitrogen, “aluminum indium gallium nitride” or “AlInGaN” refers to a material that includes aluminum, indium, gallium and nitrogen, and so on). Further, the term “high-k dielectric” refers to a material having a higher dielectric constant (k) than silicon oxide, while the term “low-k dielectric” refers to a material having a lower k than silicon oxide. The terms “substantially,” “close,” “approximately,” “near,” and “about,” generally refer to being within +/−20%, preferably within +/−10%, of a target value based on the context of a particular value as described herein or as known in the art. Similarly, terms indicating orientation of various elements, e.g., “coplanar,” “perpendicular,” “orthogonal,” “parallel,” or any other angle between the elements, generally refer to being within +/−5-20% of a target value based on the context of a particular value as described herein or as known in the art.

The terms such as “over,” “under,” “between,” and “on” as used herein refer to a relative position of one material layer or component with respect to other layers or components. For example, one layer disposed over or under another layer may be directly in contact with the other layer or may have one or more intervening layers. Moreover, one layer disposed between two layers may be directly in contact with one or both of the two layers or may have one or more intervening layers. In contrast, a first layer described to be “on” a second layer refers to a layer that is in direct contact with that second layer. Similarly, unless explicitly stated otherwise, one feature disposed between two features may be in direct contact with the adjacent features or may have one or more intervening layers.

For the purposes of the present disclosure, the phrase “A and/or B” means (A), (B), or (A and B). For the purposes of the present disclosure, the phrase “A, B, and/or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). The term “between,” when used with reference to measurement ranges, is inclusive of the ends of the measurement ranges. As used herein, the notation “A/B/C” means (A), (B), and/or (C).

The description uses the phrases “in an embodiment” or “in embodiments,” which may each refer to one or more of the same or different embodiments. Furthermore, the terms “comprising,” “including,” “having,” and the like, as used with respect to embodiments of the present disclosure, are synonymous. The disclosure may use perspective-based descriptions such as “above,” “below,” “top,” “bottom,” and “side”; such descriptions are used to facilitate the discussion and are not intended to restrict the application of disclosed embodiments. The accompanying drawings are not necessarily drawn to scale. Unless otherwise specified, the use of the ordinal adjectives “first,” “second,” and “third,” etc., to describe a common object, merely indicate that different instances of like objects are being referred to, and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking or in any other manner.

In the following detailed description, reference is made to the accompanying drawings that form a part hereof, and in which is shown, by way of illustration, embodiments that may be practiced. It is to be understood that other embodiments may be utilized, and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be taken in a limiting sense. For convenience, if a collection of drawings designated with different letters are present, e.g., FIGS. 5A-5B, such a collection may be referred to herein without the letters, e.g., as “FIG. 5.” In the drawings, same reference numerals refer to the same or analogous elements/materials shown so that, unless stated otherwise, explanations of an element/material with a given reference numeral provided in context of one of the drawings are applicable to other drawings where element/materials with the same reference numerals may be illustrated.

In the drawings, some schematic illustrations of example structures of various structures, devices, and assemblies described herein may be shown with precise right angles and straight lines, but it is to be understood that such schematic illustrations may not reflect real-life process limitations which may cause the features to not look so “ideal” when any of the structures described herein are examined using e.g., scanning electron microscopy (SEM) images or transmission electron microscope (TEM) images. In such images of real structures, possible processing defects could also be visible, e.g., not-perfectly straight edges of materials, tapered vias or other openings, inadvertent rounding of corners or variations in thicknesses of different material layers, occasional screw, edge, or combination dislocations within the crystalline region(s), and/or occasional dislocation defects of single atoms or clusters of atoms. There may be other defects not listed here but that are common within the field of device fabrication.

Various operations may be described as multiple discrete actions or operations in turn in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be construed as to imply that these operations are necessarily order dependent. In particular, these operations may not be performed in the order of presentation. Operations described may be performed in a different order from the described embodiment. Various additional operations may be performed, and/or described operations may be omitted in additional embodiments.

Various IC structures that include at least one planar III-N transistor with a wrap-around gate and/or one or more wrap-around S/D contacts as described herein may be implemented in one or more components associated with an IC or/and between various such components. In various embodiments, components associated with an IC include, for example, transistors, diodes, power sources, resistors, capacitors, inductors, sensors, transceivers, transmitters, receivers, antennas, etc. Components associated with an IC may include those that are mounted on an IC, provided as an integral part of an IC, or those connected to an IC. The IC may be either analog or digital, or may include a combination of analog and digital circuitry, and may be used in a number of applications, such as microprocessors, optoelectronics, logic blocks, audio amplifiers, etc., depending on the components associated with the IC. In some embodiments, IC structures as described herein may be included in a RFIC, which may, e.g., be included in any component associated with an IC of an RF receiver, an RF transmitter, or an RF transceiver, or any other RF device, e.g., as used in telecommunications within base stations (BS) or user equipment (UE) devices. Such components may include, but are not limited to, RF switches, power amplifiers, low-noise amplifiers, RF filters (including arrays of RF filters, or RF filter banks), upconverters, downconverters, and duplexers. In some embodiments, the IC structures as described herein may be employed as part of a chipset for executing one or more related functions in a computer.

Wrap-Around Gate and S/D Contact Schemes for a III-N Transistor

FIGS. 1A-1C provide different cross-sectional side views illustrating an IC structure 100 that includes a planar III-N transistor 102 with a wrap-around gate and wrap-around S/D contacts, according to some embodiments of the present disclosure. The cross-sectional side view of FIG. 1A is the view in the x-z plane of the example coordinate system x-y-z of FIGS. 1A-1C (the coordinate system illustrated at the bottom of FIGS. 1A-1C), with the cross-section taken along the gate length (e.g., along the plane shown in FIGS. 1B and 1C as a plane AA). The cross-sectional side view of FIG. 1B is the view in the y-z plane of the example coordinate system shown in FIGS. 1A-1C, with the cross-section taken across one example portion of a gate stack 128 (e.g., along the plane shown in FIG. 1A as a plane BB). The cross-sectional side view of FIG. 1C is the view in the y-z plane of the example coordinate system shown in FIGS. 1A-1C, with the cross-section taken across one example portion of an S/D contact 126 (e.g., along the plane shown in FIG. 1A as a plane CC). A legend provided within a dashed box at the bottom of FIGS. 1A-1C illustrates colors/patterns used to indicate some classes of materials of some of the elements shown in FIGS. 1A-1C, so that the drawings are not cluttered by too many reference numerals. For example, FIGS. 1A-1C use different colors/patterns to identify a support structure 108, an insulator 110, a III-N material 112, a polarization material 114, S/D regions 116 of the III-N transistor 102, an electrically conductive material 118 used to implement contacts to various transistor terminals, a gate dielectric material 120, and a gate electrode material 122.

The support structure 108 may be any suitable structure, e.g., a substrate, a die, or a chip, on which planar transistors as described herein may be implemented. In some embodiments, the support structure 108 may include a semiconductor, such as silicon. In other implementations, the support structure 108 may include/be alternate materials, which may or may not be combined with silicon, that include but are not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, indium gallium arsenide, gallium antimonide, or other combinations of group III-N or group IV materials.

In some embodiments, the support structure 108 may include a ceramic material, or any other non-semiconductor material. For example, in some embodiments, the support structure 108 may include glass, a combination of organic and inorganic materials, embedded portions having different materials, etc. Although a few examples of materials from which the support structure 108 may be formed are described here, any material that may serve as a foundation upon which at least one III-N transistor as described herein may be built falls within the spirit and scope of the present disclosure.

In some embodiments, an insulator 110 may be provided in various portions of the IC structure 100, e.g., encompassing various portions of the III-N transistor 102, as shown in FIG. 1. Examples of the insulator 110 may include silicon oxide, silicon nitride, aluminum oxide, silicon oxynitride, or any other suitable interlayer dielectric (ILD) materials used in semiconductor manufacturing. Although not specifically shown in FIG. 1, in some embodiments, an insulating layer, e.g., a layer of the insulator 110, may be provided between the support structure 108 and the III-N material 112. Such an insulating layer may, e.g., include an oxide isolation layer, and may be used to electrically isolate the semiconductor material of the support structure 108 from other regions of or surrounding the III-N transistor 102. Providing such an insulating layer over the support structure 108 and below the III-N transistor 102 may help mitigate the likelihood that undesirable conductive pathways will form through the support structure 108 (e.g., a conductive pathway between the S/D regions 116 of the III-N transistor 102).

In general, an insulating material such as the insulator 110 may be provided in various portions of the IC structure 100. In some embodiments, the insulator 110 may include a continuous insulator material encompassing at least portions of the III-N transistor 102. In various embodiments, an insulating material in the IC structure 100 may include different material compositions of insulating materials in different portions of the IC structure 100, e.g., the material composition of the insulator 110 used below the wrap-around gate stack 128 (e.g., below the plane from which the dimension 136, shown in FIG. 1B, is measured) may be different from the material composition of the insulator 110 used above the bottom of the wrap-around gate stack 128 (e.g., above the plane from which the dimension 136, shown in FIG. 1B, is measured).

A channel stack of the III-N transistor 102 may be considered to include a III-N material 112 and a polarization material 114.

In some embodiments, the III-N material 112 may be formed of a compound semiconductor with a first sub-lattice of at least one element from group III of the periodic table (e.g., Al, Ga, In), and a second sub-lattice of nitrogen (N). In some embodiments, the III-N material 112 may be a binary, ternary, or quaternary III-N compound semiconductor that is an alloy of two, three, or even four elements from group III of the periodic table (e.g., boron, aluminum, indium, gallium) and nitrogen.

In general, the III-N material 112 may be composed of various III-N semiconductor material systems including, for example, N-type or P-type III-N materials systems, depending on whether the III-N transistor 102 is an N-type or a P-type transistor. For some N-type transistor embodiments, the III-N material 112 may advantageously be a III-N material having a high electron mobility, such a, but not limited to GaN. For some such embodiments, the III-N material 112 may be a ternary III-N alloy, such as InGaN, or a quaternary III-N alloy, such as AlInGaN.

In some embodiments, the III-N material 112 may be formed of a highly crystalline semiconductor, e.g., of substantially a monocrystalline semiconductor (possibly with some limited amount of defects, e.g., dislocations). The quality of the III-N material 112 (e.g., in terms of defects or crystallinity) may be higher than that of other III-N materials of, or near, the III-N transistor 102 since, during the operation of the III-N transistor 102, a transistor channel will form in the III-N material 112. A portion of the III-N material 112 where a transistor channel of the III-N transistor 102 forms during operation may be referred to as a “III-N channel material/region” of the III-N transistor 102.

In some embodiments, the III-N material 112 may be an intrinsic III-N semiconductor material or alloy, not intentionally doped with any electrically active impurity. In alternate embodiments, one or more a nominal impurity dopant level may be present within the III-N material 112, for example to set a threshold voltage Vt of the III-N transistor 102, or to provide halo pocket implants, etc. In such impurity-doped embodiments however, impurity dopant level within the III-N material 112 may be relatively low, for example below 10¹⁵ dopants per cubic centimeter (cm⁻³), or below 10¹³ cm⁻³.

In various embodiments, a thickness of the III-N material 112 may be between about 5 and 2000 nanometers, including all values and ranges therein, e.g., between about 50 and 1000 nanometers, or between about 10 and 50 nanometers. Unless specified otherwise, all thicknesses described herein refer to a dimension measured in a direction perpendicular to the support structure 108 (i.e., measured along the z-axis of the example coordinate system shown in FIG. 1).

Turning now to the polarization material 114 of the channel stack of the III-N transistor 102, in general, the polarization material 114 may be a layer of a charge-inducing film of a material having larger spontaneous and/or piezoelectric polarization than that of the bulk of the III-N layer material immediately below it (e.g., the III-N material 112), creating a heterojunction (i.e., an interface that occurs between two layers or regions of semiconductors having unequal band gaps) with the III-N material 112, and leading to formation of 2 DEG at or near (e.g., immediately below) that interface, during operation of the III-N transistor 102. A dashed horizontal line shown in FIGS. 1A and 1B schematically illustrates 2 DEG that may be formed during operation of the III-N transistor 102 in an upper portion of the III-N material 112, immediately below the polarization material 114. In various embodiments, the polarization material 114 may include materials such as AlN, InAlN, AlGaN, or Al_(x)In_(y)Ga_(1-x-y)N, and may have a thickness (dimension 134 shown in FIG. 1A) between about 1 and 100 nanometers, including all values and ranges therein, e.g., between about 5 and 50 nanometers or between about 5 and 30 nanometers. The gate stack 128 may be provided in a recess in the polarization material 114, in which case a thickness of the polarization material 114 between the gate stack 128 and the III-N material 112 (dimension 138 shown in FIG. 1B) may be between about 0.1 and 50 nanometers, e.g., between about 1 and 20 nanometers, or between about 1 and 10 nanometers.

As also shown in FIG. 1, the III-N transistor 102 may include two S/D regions 116, where one of the S/D regions 116 is a source region and another one is a drain region, where the “source” and the “drain” designations may be interchangeable. As is well-known, in a transistor, S/D regions (also sometimes interchangeably referred to as “diffusion regions”) are regions that can supply charge carriers for the transistor channel (i.e., the conductive channel in the III-N material 112) of the transistor (e.g., the III-N transistor 102). In some embodiments, the S/D regions 116 may include doped semiconductor materials, such as highly doped InGaN. Often, the S/D regions may be highly doped, e.g., with dopant concentrations of at least above 1.10²⁰ cm⁻³, in order to advantageously form Ohmic contacts with the respective S/D contacts (or electrodes) of the III-N transistor 102 (e.g., S/D contacts 126 shown in FIG. 1, which could be made of the electrically conductive material 118), although these regions may also have lower dopant concentrations in some implementations. Regardless of the exact doping levels, the S/D regions 116 may be the regions having dopant concentration higher than in other regions between the source region (e.g., the S/D region 116 shown on the left side in FIG. 1) and the drain region (e.g., the S/D region 116 shown on the right side in FIG. 1), e.g., higher than in the III-N material 112. For that reason, sometimes the S/D regions are referred to as highly doped (HD) S/D regions. In further embodiments, one or more layers of metal and/or metal alloys may be used to form the S/D regions 116 in the channel stack of the transistor 102.

The electrically conductive material 118 of the S/D contacts 126 may include any suitable electrically conductive material, alloy, or a stack of multiple electrically conductive materials. In some embodiments, the electrically conductive material 118 may include one or more metals or metal alloys, with metals such as copper, ruthenium, palladium, platinum, cobalt, nickel, hafnium, zirconium, titanium, tantalum, and aluminum, tantalum nitride, titanium nitride, tungsten, doped silicon, doped germanium, or alloys and mixtures of these. In some embodiments, the electrically conductive material 118 may include one or more electrically conductive alloys, oxides, or carbides of one or more metals. In some embodiments, the electrically conductive material 118 may include a doped semiconductor, such as silicon or another semiconductor doped with an N-type dopant or a P-type dopant. Metals may provide higher conductivity, while doped semiconductors may be easier to pattern during fabrication. In some embodiments, a thickness of the electrically conductive material 118 of the S/D contacts 126 may be between about 2 nanometers and 1000 nanometers, e.g., between about 2 nanometers and 100 nanometers. FIG. 1 further illustrates that the electrically conductive material 118 may also be used to form electrical contact to the gate stack 128 of the III-N transistor 102. In general, the electrically conductive material 118 may also be used to form electrical contacts to any of the transistor terminals of the III-N transistor 102, although, in various embodiments, the exact material compositions of the electrically conductive material 118 may be different when used to implement contacts to different terminals of the III-N transistor 102.

FIG. 1 further illustrates a gate stack 128 provided over the channel portion of the III-N material 112. The gate stack 128 may include a layer of a gate dielectric material 120, and a gate electrode material 122.

The gate dielectric material 120 may be a high-k dielectric material, e.g., a material including elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in the gate dielectric material 120 may include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, tantalum oxide, tantalum silicon oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, an annealing process may be carried out on the gate dielectric material 120 during manufacture of the III-N transistor 102 to improve the quality of the gate dielectric material 120. In some embodiments, a thickness of the gate dielectric material 120 may be between about 0.5 nanometers and 3 nanometers, including all values and ranges therein, e.g., between about 1 and 3 nanometers, or between about 1 and 2 nanometers.

The gate electrode material 122 may include at least one P-type work function metal or N-type work function metal, depending on whether the III-N transistor 102 is a P-type metal-oxide-semiconductor (PMOS) transistor or an N-type metal-oxide-semiconductor (NMOS) transistor (e.g., P-type work function metal may be used as the gate electrode material 122 when the transistors 102 is a PMOS transistor and N-type work function metal may be used as the gate electrode material 122 when the III-N transistor 102 is an NMOS transistor, depending on the desired threshold voltage). For a PMOS transistor, metals that may be used for the gate electrode material 122 may include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, titanium nitride, and conductive metal oxides (e.g., ruthenium oxide). For an NMOS transistor, metals that may be used for the gate electrode material 122 include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide), and nitrides of these metals (e.g., tantalum nitride, and tantalum aluminum nitride). In some embodiments, the gate electrode material 122 may include a stack of two or more metal layers, where one or more metal layers are work function metal layers and at least one metal layer is a fill metal layer.

Further layers may be included next to the gate electrode material 122 for other purposes, such as to act as a diffusion barrier layer or/and an adhesion layer, not specifically shown in FIG. 1. Furthermore, in some embodiments, the gate dielectric material 120 and the gate electrode material 122 may be surrounded by a gate spacer, not shown in FIG. 1, configured to provide separation between the gates of different transistors. Such a gate spacer may be made of a low-k dielectric material (i.e., a dielectric material that has a lower dielectric constant (k) than silicon dioxide, which has a dielectric constant of 3.9). Examples of low-k materials that may be used as the dielectric gate spacer may include, but are not limited to, fluorine-doped silicon dioxide, carbon-doped silicon dioxide, spin-on organic polymeric dielectrics such as polyimide, polynorbornenes, benzocyclobutene, and polytetrafluoroethylene (PTFE), or spin-on silicon-based polymeric dielectric such as hydrogen silsesquioxane (HSQ) and methylsilsesquioxane (MSQ)). Other examples of low-k materials that may be used as the dielectric gate spacer include various porous dielectric materials, such as for example porous silicon dioxide or porous carbon-doped silicon dioxide, where large voids or pores are created in a dielectric in order to reduce the overall dielectric constant of the layer, since voids can have a dielectric constant of nearly 1.

The III-N transistor 102 shown in FIG. 1 is a planar transistor, with the channel stack of the transistor implemented as an island above the support structure 108. In some embodiments, a width (dimension 142 shown in FIG. 1B) of the channel stack in a direction perpendicular to a gate length (a dimension 140 shown in FIG. 1A) may be between about 20 nanometers and 1 millimeter, including all values and ranges therein, e.g., between about 50 nanometers and 500 micrometers, or between about 100 nanometers and 50 micrometers. In general, in various embodiments, the width of the channel stack in the direction perpendicular to the gate length may be between about 0.3 and 700 times the gate length, including all values and ranges therein, e.g., between about 0.5 and 100 times the gate length, or between about 0.7 and 30 times the gate length.

For such planar transistors, a wrap-around scheme for the gate stack and the S/D contacts may be particularly beneficial, details of which will now be described.

FIG. 1B illustrates that, in some embodiments of the III-N transistor 102, the gate stack 128 may at least partially wrap around an upper portion of the channel stack of the III-N material 112 and the polarization material 114. In particular, as shown in FIG. 1B, in some embodiments, the gate stack 128 may be provided not only over an upper face 152 of the channel stack (the upper face 152 being the face of the channel stack that is the farthest away from the support structure 108), but also along an upper portion of at least one of the two sidewalls 154 of the channel stack. FIG. 1B illustrates that the gate stack 128 wraps around the upper portion of each of the two sidewalls 154, the sidewalls 154 extending in the plane parallel to a plane in which the gate length 140 is measured, i.e. in two different x-z planes, opposite one another and separated by the distance 142. A portion of the gate stack 128 provided over the upper face 152 of the channel stack may be continuous with portions of the gate stack 128 provided over upper portions of the sidewalls 154. In particular, in some embodiments, the gate stack 128 may extend, from the upper face 152 of the channel stack, along at least one (but preferably both) of the sidewalls 154 to a depth (a dimension 136 shown in FIG. 1B) that is between about 2 and 100 nanometers, including all values and ranges therein, e.g., between about 4 and 50 nanometers, or between about 5 and 30 nanometers. Thus, when the gate stack 128 is implemented as a wrap-around gate stack, the gate dielectric material 120 may wrap around the upper portion of the channel stack, and the gate electrode material 122 may wrap around the gate dielectric material 120, both extending to the depth 136 below the upper face 152 of the channel stack under the upper portion of the gate stack 128. As a result, in some embodiments, a portion of the gate dielectric material 120 may be in contact with the III-N material 112 at the at least one of the two sidewall 154 of the channel stack.

Similarly, FIG. 1C illustrates that, in some embodiments of the III-N transistor 102, the S/D contact 126 (i.e., the electrically conductive material 118 forming the S/D contact 126) may at least partially wrap around an upper portion of the respective S/D region 116 to which the S/D contact 126 provides electrical connectivity to. In particular, as shown in FIG. 1C, in some embodiments, the S/D contact 126 may be provided not only over an upper face 162 of the S/D region 116 (the upper face 162 being the face of the S/D region 116 that is the farthest away from the support structure 108), but also along an upper portion of at least one of the two sidewalls 164 of the S/D region 116. FIG. 1C illustrates that the S/D contact 126 wraps around the upper portion of each of the two sidewalls 164, the sidewalls 164 extending in the plane parallel to a plane in which the gate length 140 is measured, i.e. in two different x-z planes, opposite one another and separated by the distance 142. A portion of the S/D contact 126 provided over the upper face 162 of the S/D region 116 may be continuous (also electrically continuous) with portions of the S/D contact 126 provided over upper portions of the sidewalls 164. In particular, in some embodiments, the S/D contact 126 may extend, from the upper face 162 of the S/D region 116, along at least one (but preferably both) of the sidewalls 164 to a depth (a dimension 140 shown in FIG. 1C) that is between about 2 and 150 nanometers, including all values and ranges therein, e.g., between about 4 and 75 nanometers, or between about 5 and 45 nanometers. Thus, when the S/D contact 126 is implemented as a wrap-around S/D contact, the S/D contact 126 may wrap around the upper portion of the S/D region 116 so that an upper portion of the S/D contact 126 may be in contact with the S/D region 116 at the at least one of the two sidewall 164 of the S/D region 116.

In various embodiments, the depth 144 to which the S/D contact(s) 126 extend down along the sidewall(s) 164 of the S/D regions 116 may, but does not have to, be related to the depth 136 to which the gate stack 128 extends down along the sidewall(s) 154 of the channel stack of the III-N transistor 102. When related, e.g., because at least some of the fabrication processes used in forming the gate stack 128 and the S/D contacts 126 may be shared, or performed at the same time, the depth 144 may be substantially equal to a sum of the depth 136 and the thickness of the gate dielectric material 120.

Although not specifically shown in FIG. 1C, in some embodiments, the S/D contact(s) 126 may extend down along the sidewall(s) 164 of the S/D regions 116 along the entire depth of the S/D regions 116 (FIG. 1C illustrates an embodiment where the S/D contact(s) 126 extend to a portion of the depth of the S/D regions 116). In various embodiments, each of the first and the second S/D regions 116 may extend into the channel stack of the transistor 102 to a depth (a dimension 132 shown in FIG. 1C) that is between about 8 and 200 nanometers, including all values and ranges therein, e.g., between about 10 and 150 nanometers, or between about 10 and 80 nanometers.

In some embodiments, only one of the S/D contacts 126 for the two S/D regions 116 of the transistor 102 may be implemented as a wrap-around S/D contact described above. In other embodiments, each of the S/D contacts 126 for the two S/D regions 116 of the transistor 102 may be implemented as a respective wrap-around S/D contact as described above. In various embodiments of the transistor 102, any of these embodiments may, but do not have to, be combined with the gate stack 128 being implemented as a wrap-around gate described above. Thus, in some embodiments of the transistor 102, the gate stack 128 may be implemented as a wrap-around gate as described herein but the S/D contacts 126 not implemented as wrap-around S/D contacts as described herein (e.g., the S/D contacts 126 may be implemented as any conventional S/D contacts for a planar transistor; in other embodiments of the transistor 102, one or more of the S/D contacts 126 may be implemented as wrap-around S/D contacts as described herein but the gate stack 128 not implemented as a wrap-around gate as described herein; or, in still other embodiments of the transistor 102, the gate stack 128 may be implemented as a wrap-around gate as described herein and one or both of the S/D contacts 126 may be implemented as wrap-around S/D contacts as described herein.

Although not specifically shown in FIG. 1, the IC structure 100 may further include additional transistors similar to the III-N transistor 102, described above.

In some embodiments, the IC structure 100 may be included in, or used to implement at least a portion of an RF FE. In some embodiments, the III-N transistor 102 of the IC structure 100 may be included in, or used to implement at least a portion of an RF circuit or a part of a power circuit included in the IC structure.

Wrap-Around Gate and S/D Contact Schemes for a Non-III-N Transistor

Wrap-around gate and S/D contact schemes as described above may be particularly beneficial for planar III-N transistors in that it may optimize the use of the 2 DEG, which is two-dimensional (i.e., planar-like) by nature. However, in general, the wrap-around gate and S/D contact schemes as described herein are applicable to non-III-N planar field effect transistors (FETs), all of which being within the scope of the present disclosure. Thus, in some embodiments of the IC structure 100, the transistor 102 described above may be a transistor implementing any other semiconductor material besides a III-N material, in which the channel stack of the transistor may not include the polarization material 114 as described above, the III-N material 112 described above would be replaced with a suitable other channel material, and the material of the S/D regions 116 might also be replaced with a suitable other S/D region material. The rest of the descriptions provided above would be applicable to such non-III-N transistor embodiments. Some example materials which may be used as the non-III-N semiconductor material of the channel stack of the transistor 102 described above and may serve as a channel material of the non-III-N transistor 102 will now be described.

In various embodiments, the non-III-N semiconductor material of the channel stack of the transistor 102 described above may be composed of semiconductor material systems including, for example, N-type or P-type materials systems. In some embodiments, such a non-III-N semiconductor material may be formed of a monocrystalline semiconductor. In some embodiments, such a non-III-N semiconductor material may have a thickness between about 5 and 10000 nanometers, including all values and ranges therein, e.g., between about 10 and 500 nanometers, or between about 10 and 50 nanometers.

In some embodiments, the support structure over which such a non-III-N semiconductor material may be provided may be any structure suitable for supporting the non-III-N semiconductor material. In some embodiments, such a support structure may include a semiconductor, such as silicon, and the non-III-N semiconductor material of the channel stack of the transistor 102 described above may be an upper layer of said semiconductor (e.g., the non-III-N semiconductor material of the channel stack of the transistor 102 described above may be silicon, e.g., an upper layer of silicon of a silicon substrate). Thus, in some implementations, such a non-III-N semiconductor material may be viewed as a part of the support structure over which it is provided, or as a part of the crystalline semiconductor upper part of such support structure.

In some embodiments, the non-III-N semiconductor material of the channel stack of the transistor 102 described above may be/include an intrinsic IV or III-V semiconductor material or alloy, not intentionally doped with any electrically active impurity. In alternate embodiments, nominal impurity dopant levels may be present within such a non-III-N semiconductor material, for example to set a threshold voltage Vt, or to provide halo pocket implants, etc. In such impurity-doped embodiments however, impurity dopant level within the non-III-N semiconductor material may be relatively low, for example below about 10¹⁵ cm⁻³, and advantageously below 10¹³ cm⁻³.

In some embodiments, the non-III-N semiconductor material of the channel stack of the transistor 102 described above may be formed of a compound semiconductor with a first sub-lattice of at least one element from group III of the periodic table (e.g., Al, Ga, In), and a second sub-lattice of at least one element of group V of the periodic table (e.g., P, As, Sb). In some embodiments, such a non-III-N semiconductor material may be a binary, ternary, or quaternary III-V compound semiconductor that is an alloy of two, three, or even four elements from groups III and V of the periodic table, including boron, aluminum, indium, gallium, nitrogen, arsenic, phosphorus, antimony, and bismuth.

For exemplary P-type transistor embodiments, the non-III-N semiconductor material of the channel stack of the transistor 102 described above may advantageously be a group IV material having a high hole mobility, such as, but not limited to, Ge or a Ge-rich SiGe alloy. For some exemplary embodiments, such a non-III-N semiconductor material may have a Ge content between 0.6 and 0.9, and advantageously is at least 0.7.

For exemplary N-type transistor embodiments, the non-III-N semiconductor material of the channel stack of the transistor 102 described above may advantageously be a III-V material having a high electron mobility, such as, but not limited to InGaAs, InP, InSb, and InAs. For some such embodiments, such a non-III-N semiconductor material may be a ternary III-V alloy, such as InGaAs or GaAsSb. For some In_(x)Ga_(1-x)As fin embodiments, In content in the non-III-N semiconductor material may be between 0.6 and 0.9, and advantageously at least 0.7 (e.g., In_(0.7)Ga_(0.3)As).

In some embodiments, the non-III-N semiconductor material of the channel stack of the transistor 102 described above may be a thin-film material, in which embodiments the planar transistor 102 could be a thin-film transistor (TFT). A TFT may be a special kind of a FET, made by depositing a thin film of an active semiconductor material, as well as a dielectric layer and metallic contacts, over a support structure that may be a non-conducting (and non-semiconducting) support structure. During operation of a TFT, at least a portion of the active semiconductor material forms a channel of the TFT, and, therefore, the thin film of such active semiconductor material may be referred to as a “TFT channel material.” In various such embodiments, the thin-film non-III-N semiconductor material of the channel stack of the transistor 102 described above may include a high mobility oxide semiconductor material, such as tin oxide, antimony oxide, indium oxide, indium tin oxide, titanium oxide, zinc oxide, indium zinc oxide, indium gallium zinc oxide (IGZO), gallium oxide, titanium oxynitride, ruthenium oxide, or tungsten oxide. In general, the non-III-N semiconductor material of the channel stack of the transistor 102 described above may include one or more of tin oxide, cobalt oxide, copper oxide, antimony oxide, ruthenium oxide, tungsten oxide, zinc oxide, gallium oxide, titanium oxide, indium oxide, titanium oxynitride, indium tin oxide, indium zinc oxide, nickel oxide, niobium oxide, copper peroxide, IGZO, indium telluride, molybdenite, molybdenum diselenide, tungsten diselenide, tungsten disulfide, N- or P-type amorphous or polycrystalline silicon, germanium, indium gallium arsenide, silicon germanium, gallium nitride, aluminum gallium nitride, indium phosphide, and black phosphorus, each of which may possibly be doped with one or more of gallium, indium, aluminum, fluorine, boron, phosphorus, arsenic, nitrogen, tantalum, tungsten, and magnesium, etc.

Wrap-Around Gate and S/D Contact Schemes for a III-N Transistor with a Buffer Layer

In some embodiments, current leakage may further be improved by providing a back barrier in a form of a buffer layer, as illustrated in FIGS. 2A-2C.

FIGS. 2A-2C illustrate different cross-sectional side views illustrating an IC structure 200 that includes a planar III-N transistor 102 with a wrap-around gate stack 128, one or more wrap-around S/D contacts 126, and further includes a buffer material 202, according to some embodiments of the present disclosure. The IC structure 200 is similar to the IC structure 100 where the same numbers illustrate analogous elements and the cross-sectional views of FIGS. 2A-2C are analogous to those of FIGS. 1A-1C, respectively. Therefore, in the interests of brevity, descriptions provided for the IC structure 100 shown in FIG. 1 are assumed to be applicable to the IC structure 200 shown in FIG. 2 and are not repeated herein, and only the differences between these IC structures are described below.

In particular, FIGS. 2A-2C illustrate that, in some embodiments, the IC structure 200 may further include a buffer material 202 between the channel stack of the transistor 102 and the support structure 108 (e.g., between the III-N material 112 and the support structure 108). In some embodiments, the buffer material 202 may be a layer of a semiconductor material that has a band gap larger than that of the III-N material 112, so that the buffer material 202 can serve to prevent current leakage from the III-N transistor 102 to the support structure 108. Furthermore, a properly selected semiconductor for the buffer material 202 may enable better epitaxy of the III-N material 112 thereon, e.g., it may improve epitaxial growth of the III-N material 112, for instance in terms of a bridge lattice constant or amount of defects. For example, a semiconductor that includes aluminum, gallium, and nitrogen (e.g., AlGaN) or a semiconductor that includes aluminum and nitrogen (e.g., AlN) may be used as the buffer material 202 when the III-N material 112 is a semiconductor that includes gallium and nitrogen (e.g., GaN). Other examples of materials for the buffer material 202 may include materials typically used as ILD, described above, such as oxide isolation layers, e.g., silicon oxide, silicon nitride, aluminum oxide, and/or silicon oxynitride. When implemented in the III-N transistor 102, the buffer material 202 may have a thickness between about 100 and 5000 nm, including all values and ranges therein, e.g., between about 200 and 1500 nanometers, or between about 250 and 800 nanometers.

Further Embodiments with Wrap-Around Gate and S/D Contact Schemes

The IC structures 100/200 illustrated in FIGS. 1-2 do not represent an exhaustive set of assemblies in which one or more planar transistors with wrap-around gates and/or one or more wrap-around S/D contacts may be provided as described herein, but merely provide examples of such structures/assemblies. Although particular arrangements of materials are discussed with reference to FIGS. 1-2, intermediate materials may be included in various portions of these figures. Note that FIGS. 1-2 are intended to show relative arrangements of some of the components therein, and that various device components of these figures may include other components that are not specifically illustrated, e.g., various interfacial layers or various additional layers or elements. For example, although not specifically shown, the IC structures 100, 200 may include a solder resist material (e.g., polyimide or similar material) and one or more bond pads formed on upper-most interconnect layer of the IC structure, e.g., at the top of the IC structures 100/200 shown in FIGS. 1-2. The bond pads may be electrically coupled with a further interconnect structure and configured to route the electrical signals between the III-N transistor 102 and other external devices. For example, solder bonds may be formed on the one or more bond pads to mechanically and/or electrically couple a chip including the IC structure 100/200 with another component (e.g., a circuit board). The IC structure 100/200 may have other alternative configurations to route the electrical signals from the interconnect layers, e.g., the bond pads described above may be replaced by or may further include other analogous features (e.g., posts) that route the electrical signals to external components.

Additionally, although some elements of the IC structures are illustrated in FIGS. 1-2 as being planar rectangles or formed of rectangular solids, this is simply for ease of illustration, and embodiments of various ones of these elements may be curved, rounded, or otherwise irregularly shaped as dictated by, and sometimes inevitable due to, the manufacturing processes used to fabricate semiconductor device assemblies. For example, while FIGS. 1-2 may illustrate various elements, e.g., the S/D regions 116, the S/D contacts 126, etc., as having perfectly straight sidewall profiles (e.g., profiles where the sidewalls extend perpendicularly to the support structure 108), these idealistic profiles may not always be achievable in real-world manufacturing processes. Namely, while designed to have straight sidewall profiles, real-world openings which may be formed as a part of fabricating various elements of the IC structures shown in FIGS. 1-2 may end up having either so-called “re-entrant” profiles, where the width at the top of the opening is smaller than the width at the bottom of the opening, or “non-re-entrant” profile, where the width at the top of the opening is larger than the width at the bottom of the opening. Oftentimes, as a result of a real-world opening not having perfectly straight sidewalls, imperfections may form within the materials filling the opening. For example, typical for re-entrant profiles, a void may be formed in the center of the opening, where the growth of a given material filling the opening pinches off at the top of the opening. Therefore, present descriptions of various embodiments of integrating wrap-around gates with planar III-N transistors are equally applicable to embodiments where various elements of such integrated structures look different from those shown in the figures due to manufacturing processes used to form them.

Inspection of layout and mask data and reverse engineering of parts of a device to reconstruct the circuit using e.g., optical microscopy, TEM, or SEM, and/or inspection of a cross-section of a device to detect the shape and the location of various device elements described herein using e.g., Physical Failure Analysis (PFA) would allow determination of the integration of wrap-around gates with planar III-N transistors as described herein.

Manufacturing Planar Transistors with Wrap-Around Gates and/or S/D Contacts

The IC structures implementing one or more planar transistors with wrap-around gates and/or one or more wrap-around S/D contacts as described herein may be manufactured using any suitable techniques. FIG. 3 illustrates one example of such a method. However, other examples of manufacturing any of the IC structures described herein, as well as larger devices and assemblies that include such structures (e.g., as shown in FIGS. 6-9) are also within the scope of the present disclosure.

FIG. 3 is a flow diagram of an example method 300 of manufacturing an IC structure that includes a III-N transistor with a wrap-around gate and/or one or more wrap-around S/D contacts, in accordance with various embodiments of the present disclosure.

Although the operations of the method 300 are illustrated once each and in a particular order, the operations may be performed in any suitable order and repeated as desired. For example, one or more operations may be performed in parallel to manufacture, substantially simultaneously, multiple III-N transistors with wrap-around gates and/or one or more wrap-around S/D contacts as described herein. In another example, the operations may be performed in a different order to reflect the structure of a particular device assembly in which one or more planar III-N transistors with wrap-around gates and/or one or more wrap-around S/D contacts as described herein will be included.

In addition, the example manufacturing method 300 may include other operations not specifically shown in FIG. 3, such as various cleaning or planarization operations as known in the art. For example, in some embodiments, the support structure 108, as well as layers of various other materials subsequently deposited thereon, may be cleaned prior to, after, or during any of the processes of the method 300 described herein, e.g., to remove oxides, surface-bound organic and metallic contaminants, as well as subsurface contamination. In some embodiments, cleaning may be carried out using e.g., a chemical solutions (such as peroxide), and/or with ultraviolet (UV) radiation combined with ozone, and/or oxidizing the surface (e.g., using thermal oxidation) then removing the oxide (e.g., using hydrofluoric acid (HF)). In another example, the structures/assemblies described herein may be planarized prior to, after, or during any of the processes of the method 300 described herein, e.g., to remove overburden or excess materials. In some embodiments, planarization may be carried out using either wet or dry planarization processes, e.g., planarization be a chemical mechanical planarization (CMP), which may be understood as a process that utilizes a polishing surface, an abrasive and a slurry to remove the overburden and planarize the surface.

Various operations of the method 300 may be illustrated with reference to the example embodiments shown in FIGS. 4A-4E, illustrating fabrication of an IC structure as shown in FIG. 1, but the method 300 may be used to manufacture any suitable IC structures having one or more planar transistors with wrap-around gates and/or one or more wrap-around S/D contacts according to any other embodiments of the present disclosure. FIGS. 4A-4E illustrate cross-sectional side views, where each of FIGS. 4A-4E illustrates two views analogous to the views shown in FIGS. 1A and 1B, in various example stages in the manufacture of an IC structure using the method of FIG. 3 in accordance with some embodiments of the present disclosure.

The method 300 may begin with providing a channel stack over a support structure (process 302 shown in FIG. 3, a result of which is illustrated with an IC structure 402 shown in FIG. 4A). The IC structure 402 illustrates that the support structure provided in 302 may be the support structure 108 as described above. The IC structure 402 further illustrates that the channel stack provided over the support structure in 302 may include the III-N material 112 deposited over the support structure 108, and the polarization material 114 deposited over the III-N material 112.

In some embodiments, the process 302 may include epitaxially growing various transistor films, e.g., for forming the III-N material 112 and the polarization material 114. In this context, “epitaxial growth” refers to the deposition of crystalline overlayers in the form of the desired materials. The epitaxial growth of various layers of the process 302 may be carried out using any known gaseous or liquid precursors for forming the desired material layers.

In some embodiments, the process 302 may include patterning to shape the channel stack in the desired geometry, e.g., as an island (e.g., as shown in the cross-section on the right side of FIG. 4A), so that the channel stack is surrounded by an insulator, e.g. the insulator 110. Any suitable deposition techniques may be used to deposit the insulator 110, such as, but not limited to, spin-coating, dip-coating, atomic layer deposition (ALD), physical vapor deposition (PVD) (e.g., evaporative deposition, magnetron sputtering, or e-beam deposition), or chemical vapor deposition (CVD). Examples patterning techniques which may be used in the process 302 may include, but are not limited to, photolithographic or electron-beam (e-beam) patterning, possibly in conjunction with a suitable etching technique, e.g., a dry etch, such as RF reactive ion etch (RIE) or inductively coupled plasma (ICP) RIE. In various embodiments, any of the etches performed in the process 302 may include an anisotropic etch. Some anisotropic etches may use etchants that take the form of a chemically active ionized gas (e.g., plasma). Some such etchants may have a bromine-based chemistry or a chlorine-based chemistry. In some embodiments, during any of the etches of the process 302, the IC structure may be heated to elevated temperatures, e.g., to temperatures between about room temperature and 200 degrees Celsius, including all values and ranges therein, to promote that byproducts of the etch are made sufficiently volatile to be removed from the surface.

The method 300 may then proceed with providing S/D regions in the channel stack provided in 302 (process 304 shown in FIG. 3, a result of which is illustrated with an IC structure 404 shown in FIG. 4B). The IC structure 404 illustrates that the process 304 may include forming the S/D regions 116, e.g., using any of the techniques described above, possibly using any suitable patterning techniques, e.g., as described above, to achieve the desired geometry for the S/D regions.

Once the S/D regions have been formed, the method 300 may proceed with performing a recess of the dielectric material around upper portions of the sidewalls of the channel stack which are in the opposite planes parallel to the plane connecting the first and second S/D regions formed in 304 (the latter plane being a plane perpendicular to the support structure 108) (process 306 shown in FIG. 3, a result of which is illustrated with an IC structure 406 shown in FIG. 4C). The IC structure 406 illustrates that the process 306 may expose surfaces of upper portions 454 of the sidewalls 154 of the channel stack formed in 302. In some embodiments, the process 306 may include performing a suitable etch, e.g., any of the etches described above with reference to the process 302.

The method 300 may then proceed with defining a region for forming a gate stack for the future transistor (process 308 shown in FIG. 3, a result of which is illustrated with an IC structure 408 shown in FIG. 4D). The IC structure 408 illustrates that the process 308 may include forming an opening 458 for forming the gate stack 128 therein in a subsequent process. The process 308 may include any suitable techniques for forming an opening for the gate stack, e.g., replacement gate techniques, possibly using any suitable patterning techniques, e.g., as described above, to achieve the desired geometry for the opening 458.

The method 300 may then proceed with providing a gate stack in the region defined in the process 308 (process 310 shown in FIG. 3, a result of which is illustrated with an IC structure 410 shown in FIG. 4E). The IC structure 410 illustrates that the process 310 may include forming the gate stack 128 in the opening 458, where the gate stack 128 is a wrap-around gate stack as described above. The process 310 may include any suitable techniques for depositing the gate dielectric of the gate stack (e.g., using a conformal deposition process such as ALD), and then depositing the gate electrode material over the gate dielectric.

The method 300 may also include providing S/D contacts to form electrical contacts with the S/D regions provided in the process 304 (process 312 shown in FIG. 3, a result of which is not illustrated in FIGS. 4A-4E because the result may be the IC structure as shown in FIG. 1). Examples of deposition techniques that may be used to provide S/D contacts in the process 312 include, but are not limited to, ALD, PVD, CVD, or electroplating.

Example Structures and Devices with Planar Transistors with Wrap-Around Dates and/or S/D Contacts

IC structures that include one or more planar transistors with wrap-around gates and/or one or more wrap-around S/D contacts as disclosed herein may be included in any suitable electronic device. FIGS. 5-9 illustrate various examples of devices and components that may include one or more planar transistors integrated with wrap-around gates and/or one or more wrap-around S/D contacts as disclosed herein.

FIGS. 5A-5B are top views of a wafer 2000 and dies 2002 that may include one or more planar transistors with wrap-around gates and/or one or more wrap-around S/D contacts in accordance with any of the embodiments disclosed herein. In some embodiments, the dies 2002 may be included in an IC package, in accordance with any of the embodiments disclosed herein. For example, any of the dies 2002 may serve as any of the dies 2256 in an IC package 2200 shown in FIG. 6. The wafer 2000 may be composed of semiconductor material and may include one or more dies 2002 having IC structures formed on a surface of the wafer 2000. Each of the dies 2002 may be a repeating unit of a semiconductor product that includes any suitable IC (e.g., ICs including one or more planar transistors with wrap-around gates and/or one or more wrap-around S/D contacts as described herein). After the fabrication of the semiconductor product is complete (e.g., after manufacture of one or more planar transistors with wrap-around gates and/or one or more wrap-around S/D contacts as described herein, e.g., after manufacture of any embodiment of the IC structures 100/200 described herein), the wafer 2000 may undergo a singulation process in which each of the dies 2002 is separated from one another to provide discrete “chips” of the semiconductor product. In particular, devices that include one or more planar transistors with wrap-around gates and/or one or more wrap-around S/D contacts as disclosed herein may take the form of the wafer 2000 (e.g., not singulated) or the form of the die 2002 (e.g., singulated). The die 2002 may include one or more planar transistors (e.g., one or more III-N transistors 102 as described herein) as well as, optionally, supporting circuitry to route electrical signals to the planar transistors, as well as any other IC components. In some embodiments, the wafer 2000 or the die 2002 may implement an RF FE device, a memory device (e.g., a static random-access memory (SRAM) device), a logic device (e.g., an AND, OR, NAND, or NOR gate), or any other suitable circuit element. Multiple ones of these devices may be combined on a single die 2002.

FIG. 6 is a side, cross-sectional view of an example IC package 2200 that may include one or more IC structures having one or more planar transistors integrated with wrap-around gates and/or one or more wrap-around S/D contacts in accordance with any of the embodiments disclosed herein. In some embodiments, the IC package 2200 may be a system-in-package (SiP).

As shown in FIG. 6, the IC package 2200 may include a package substrate 2252. The package substrate 2252 may be formed of a dielectric material (e.g., a ceramic, a glass, a combination of organic and inorganic materials, a buildup film, an epoxy film having filler particles therein, etc., and may have embedded portions having different materials), and may have conductive pathways extending through the dielectric material between the face 2272 and the face 2274, or between different locations on the face 2272, and/or between different locations on the face 2274.

The package substrate 2252 may include conductive contacts 2263 that are coupled to conductive pathways 2262 through the package substrate 2252, allowing circuitry within the dies 2256 and/or the interposer 2257 to electrically couple to various ones of the conductive contacts 2264 (or to other devices included in the package substrate 2252, not shown).

The IC package 2200 may include an interposer 2257 coupled to the package substrate 2252 via conductive contacts 2261 of the interposer 2257, first-level interconnects 2265, and the conductive contacts 2263 of the package substrate 2252. The first-level interconnects 2265 illustrated in FIG. 6 are solder bumps, but any suitable first-level interconnects 2265 may be used. In some embodiments, no interposer 2257 may be included in the IC package 2200; instead, the dies 2256 may be coupled directly to the conductive contacts 2263 at the face 2272 by first-level interconnects 2265.

The IC package 2200 may include one or more dies 2256 coupled to the interposer 2257 via conductive contacts 2254 of the dies 2256, first-level interconnects 2258, and conductive contacts 2260 of the interposer 2257. The conductive contacts 2260 may be coupled to conductive pathways (not shown) through the interposer 2257, allowing circuitry within the dies 2256 to electrically couple to various ones of the conductive contacts 2261 (or to other devices included in the interposer 2257, not shown). The first-level interconnects 2258 illustrated in FIG. 6 are solder bumps, but any suitable first-level interconnects 2258 may be used. As used herein, a “conductive contact” may refer to a portion of electrically conductive material (e.g., metal) serving as an interface between different components; conductive contacts may be recessed in, flush with, or extending away from a surface of a component, and may take any suitable form (e.g., a conductive pad or socket).

In some embodiments, an underfill material 2266 may be disposed between the package substrate 2252 and the interposer 2257 around the first-level interconnects 2265, and a mold compound 2268 may be disposed around the dies 2256 and the interposer 2257 and in contact with the package substrate 2252. In some embodiments, the underfill material 2266 may be the same as the mold compound 2268. Example materials that may be used for the underfill material 2266 and the mold compound 2268 are epoxy mold materials, as suitable. Second-level interconnects 2270 may be coupled to the conductive contacts 2264. The second-level interconnects 2270 illustrated in FIG. 6 are solder balls (e.g., for a ball grid array arrangement), but any suitable second-level interconnects 22770 may be used (e.g., pins in a pin grid array arrangement or lands in a land grid array arrangement). The second-level interconnects 2270 may be used to couple the IC package 2200 to another component, such as a circuit board (e.g., a motherboard), an interposer, or another IC package, as known in the art and as discussed below with reference to FIG. 7.

The dies 2256 may take the form of any of the embodiments of the die 2002 discussed herein and may include any of the embodiments of an IC structure having one or more planar transistors with wrap-around gates and/or one or more wrap-around S/D contacts, e.g., any of the IC structures 100 or 200, described herein. In embodiments in which the IC package 2200 includes multiple dies 2256, the IC package 2200 may be referred to as a multi-chip package (MCP). The dies 2256 may include circuitry to perform any desired functionality. For example, one or more of the dies 2256 may be RF FE dies, including one or more planar transistors with wrap-around gates and/or one or more wrap-around S/D contacts in a single die as described herein, one or more of the dies 2256 may be logic dies (e.g., silicon-based dies), one or more of the dies 2256 may be memory dies (e.g., high bandwidth memory), etc. In some embodiments, any of the dies 2256 may include one or more planar transistors with wrap-around gates and/or one or more wrap-around S/D contacts, e.g., as discussed above; in some embodiments, at least some of the dies 2256 may not include any planar transistors with wrap-around gates and/or one or more wrap-around S/D contacts.

The IC package 2200 illustrated in FIG. 6 may be a flip chip package, although other package architectures may be used. For example, the IC package 2200 may be a ball grid array (BGA) package, such as an embedded wafer-level ball grid array (eWLB) package. In another example, the IC package 2200 may be a wafer-level chip scale package (WLCSP) or a panel fan-out (FO) package. Although two dies 2256 are illustrated in the IC package 2200 of FIG. 6, an IC package 2200 may include any desired number of the dies 2256. An IC package 2200 may include additional passive components, such as surface-mount resistors, capacitors, and inductors disposed on the first face 2272 or the second face 2274 of the package substrate 2252, or on either face of the interposer 2257. More generally, an IC package 2200 may include any other active or passive components known in the art.

FIG. 7 is a cross-sectional side view of an IC device assembly 2300 that may include components having one or more IC structures implementing one or more planar transistors with wrap-around gates and/or one or more wrap-around S/D contacts in accordance with any of the embodiments disclosed herein. The IC device assembly 2300 includes a number of components disposed on a circuit board 2302 (which may be, e.g., a motherboard). The IC device assembly 2300 includes components disposed on a first face 2340 of the circuit board 2302 and an opposing second face 2342 of the circuit board 2302; generally, components may be disposed on one or both faces 2340 and 2342. In particular, any suitable ones of the components of the IC device assembly 2300 may include any of the IC structures implementing one or more planar transistors with wrap-around gates and/or one or more wrap-around S/D contacts in accordance with any of the embodiments disclosed herein; e.g., any of the IC packages discussed below with reference to the IC device assembly 2300 may take the form of any of the embodiments of the IC package 2200 discussed above with reference to FIG. 6 (e.g., may include one or more planar transistors with wrap-around gates and/or one or more wrap-around S/D contacts in/on a die 2256).

In some embodiments, the circuit board 2302 may be a printed circuit board (PCB) including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals (optionally in conjunction with other metal layers) between the components coupled to the circuit board 2302. In other embodiments, the circuit board 2302 may be a non-PCB substrate.

The IC device assembly 2300 illustrated in FIG. 7 includes a package-on-interposer structure 2336 coupled to the first face 2340 of the circuit board 2302 by coupling components 2316. The coupling components 2316 may electrically and mechanically couple the package-on-interposer structure 2336 to the circuit board 2302, and may include solder balls (e.g., as shown in FIG. 7), male and female portions of a socket, an adhesive, an underfill material, and/or any other suitable electrical and/or mechanical coupling structure.

The package-on-interposer structure 2336 may include an IC package 2320 coupled to an interposer 2304 by coupling components 2318. The coupling components 2318 may take any suitable form for the application, such as the forms discussed above with reference to the coupling components 2316. The IC package 2320 may be or include, for example, a die (the die 2002 of FIG. 5B), an IC device (e.g., the IC structure of FIGS. 1-2), or any other suitable component. In particular, the IC package 2320 may include one or more planar transistors with wrap-around gates and/or one or more wrap-around S/D contacts as described herein. Although a single IC package 2320 is shown in FIG. 7, multiple IC packages may be coupled to the interposer 2304; indeed, additional interposers may be coupled to the interposer 2304. The interposer 2304 may provide an intervening substrate used to bridge the circuit board 2302 and the IC package 2320. Generally, the interposer 2304 may spread a connection to a wider pitch or reroute a connection to a different connection. For example, the interposer 2304 may couple the IC package 2320 (e.g., a die) to a BGA of the coupling components 2316 for coupling to the circuit board 2302. In the embodiment illustrated in FIG. 7, the IC package 2320 and the circuit board 2302 are attached to opposing sides of the interposer 2304; in other embodiments, the IC package 2320 and the circuit board 2302 may be attached to a same side of the interposer 2304. In some embodiments, three or more components may be interconnected by way of the interposer 2304.

The interposer 2304 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In some implementations, the interposer 2304 may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials. The interposer 2304 may include metal interconnects 2308 and vias 2310, including but not limited to through-silicon vias (TSVs) 2306. The interposer 2304 may further include embedded devices 2314, including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) protection devices, and memory devices. More complex devices such as further RF devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices may also be formed on the interposer 2304. In some embodiments, the IC structures implementing one or more planar transistors with wrap-around gates and/or one or more wrap-around S/D contacts as described herein may also be implemented in/on the interposer 2304. The package-on-interposer structure 2336 may take the form of any of the package-on-interposer structures known in the art.

The IC device assembly 2300 may include an IC package 2324 coupled to the first face 2340 of the circuit board 2302 by coupling components 2322. The coupling components 2322 may take the form of any of the embodiments discussed above with reference to the coupling components 2316, and the IC package 2324 may take the form of any of the embodiments discussed above with reference to the IC package 2320.

The IC device assembly 2300 illustrated in FIG. 7 includes a package-on-package structure 2334 coupled to the second face 2342 of the circuit board 2302 by coupling components 2328. The package-on-package structure 2334 may include an IC package 2326 and an IC package 2332 coupled together by coupling components 2330 such that the IC package 2326 is disposed between the circuit board 2302 and the IC package 2332. The coupling components 2328 and 2330 may take the form of any of the embodiments of the coupling components 2316 discussed above, and the IC packages 2326 and 2332 may take the form of any of the embodiments of the IC package 2320 discussed above. The package-on-package structure 2334 may be configured in accordance with any of the package-on-package structures known in the art.

FIG. 8 is a block diagram of an example computing device 2400 that may include one or more components with one or more IC structures having one or more planar transistors integrated with wrap-around gates and/or one or more wrap-around S/D contacts in accordance with any of the embodiments disclosed herein. For example, any suitable ones of the components of the computing device 2400 may include a die (e.g., the die 2002 (FIG. 5B)) including one or more planar transistors with wrap-around gates and/or one or more wrap-around S/D contacts in accordance with any of the embodiments disclosed herein. Any of the components of the computing device 2400 may include an IC device (e.g., any embodiment of the IC structure of FIGS. 1-2) and/or an IC package 2200 (FIG. 6). Any of the components of the computing device 2400 may include an IC device assembly 2300 (FIG. 7).

A number of components are illustrated in FIG. 8 as included in the computing device 2400, but any one or more of these components may be omitted or duplicated, as suitable for the application. In some embodiments, some or all of the components included in the computing device 2400 may be attached to one or more motherboards. In some embodiments, some or all of these components are fabricated onto a single SoC die.

Additionally, in various embodiments, the computing device 2400 may not include one or more of the components illustrated in FIG. 8, but the computing device 2400 may include interface circuitry for coupling to the one or more components. For example, the computing device 2400 may not include a display device 2406, but may include display device interface circuitry (e.g., a connector and driver circuitry) to which a display device 2406 may be coupled. In another set of examples, the computing device 2400 may not include an audio input device 2418 or an audio output device 2408, but may include audio input or output device interface circuitry (e.g., connectors and supporting circuitry) to which an audio input device 2418 or audio output device 2408 may be coupled.

The computing device 2400 may include a processing device 2402 (e.g., one or more processing devices). As used herein, the term “processing device” or “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory. The processing device 2402 may include one or more digital signal processors (DSPs), application-specific ICs (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptoprocessors (specialized processors that execute cryptographic algorithms within hardware), server processors, or any other suitable processing devices. The computing device 2400 may include a memory 2404, which may itself include one or more memory devices such as volatile memory (e.g., DRAM), nonvolatile memory (e.g., read-only memory (ROM)), flash memory, solid-state memory, and/or a hard drive. In some embodiments, the memory 2404 may include memory that shares a die with the processing device 2402. This memory may be used as cache memory and may include, e.g., eDRAM, and/or spin transfer torque magnetic random-access memory (STT-M RAM).

In some embodiments, the computing device 2400 may include a communication chip 2412 (e.g., one or more communication chips). For example, the communication chip 2412 may be configured for managing wireless communications for the transfer of data to and from the computing device 2400. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a nonsolid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not.

The communication chip 2412 may implement any of a number of wireless standards or protocols, including but not limited to Institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 Amendment), Long-Term Evolution (LTE) project along with any amendments, updates, and/or revisions (e.g., advanced LTE project, ultramobile broadband (UMB) project (also referred to as “3GPP2”), etc.). IEEE 802.16 compatible Broadband Wireless Access (BWA) networks are generally referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for Microwave Access, which is a certification mark for products that pass conformity and interoperability tests for the IEEE 802.16 standards. The communication chip 2412 may operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication chip 2412 may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip 2412 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), and derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The communication chip 2412 may operate in accordance with other wireless protocols in other embodiments. The computing device 2400 may include an antenna 2422 to facilitate wireless communications and/or to receive other wireless communications (such as AM or FM radio transmissions).

In some embodiments, the communication chip 2412 may manage wired communications, such as electrical, optical, or any other suitable communication protocols (e.g., the Ethernet). As noted above, the communication chip 2412 may include multiple communication chips. For instance, a first communication chip 2412 may be dedicated to shorter-range wireless communications such as Wi-Fi or Bluetooth, and a second communication chip 2412 may be dedicated to longer-range wireless communications such as global positioning system (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, a first communication chip 2412 may be dedicated to wireless communications, and a second communication chip 2412 may be dedicated to wired communications.

In various embodiments, IC structures as described herein may be particularly advantageous for use within the one or more communication chips 2412, described above. For example, such IC structures may be used to implement one or more of power amplifiers, low-noise amplifiers, filters (including arrays of filters and filter banks), switches, upconverters, downconverters, duplexers, and logic circuitry (e.g., control logic) implementing a variety of transistors, e.g., as a part of implementing an RF transmitter, an RF receiver, or an RF transceiver.

The computing device 2400 may include battery/power circuitry 2414. The battery/power circuitry 2414 may include one or more energy storage devices (e.g., batteries or capacitors) and/or circuitry for coupling components of the computing device 2400 to an energy source separate from the computing device 2400 (e.g., AC line power).

The computing device 2400 may include a display device 2406 (or corresponding interface circuitry, as discussed above). The display device 2406 may include any visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display, for example.

The computing device 2400 may include an audio output device 2408 (or corresponding interface circuitry, as discussed above). The audio output device 2408 may include any device that generates an audible indicator, such as speakers, headsets, or earbuds, for example.

The computing device 2400 may include an audio input device 2418 (or corresponding interface circuitry, as discussed above). The audio input device 2418 may include any device that generates a signal representative of a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments having a musical instrument digital interface (MIDI) output).

The computing device 2400 may include a GPS device 2416 (or corresponding interface circuitry, as discussed above). The GPS device 2416 may be in communication with a satellite-based system and may receive a location of the computing device 2400, as known in the art.

The computing device 2400 may include an other output device 2410 (or corresponding interface circuitry, as discussed above). Examples of the other output device 2410 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.

The computing device 2400 may include an other input device 2420 (or corresponding interface circuitry, as discussed above). Examples of the other input device 2420 may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a bar code reader, a Quick Response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.

The computing device 2400 may have any desired form factor, such as a handheld or mobile computing device (e.g., a cell phone, a smart phone, a mobile internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultramobile personal computer, etc.), a desktop computing device, a server or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable computing device. In some embodiments, the computing device 2400 may be any other electronic device that processes data.

FIG. 9 is a block diagram of an example RF device 2500 that may include one or more components with one or more IC structures having one or more planar transistors with wrap-around gates and/or one or more wrap-around S/D contacts in accordance with any of the embodiments disclosed herein. For example, any suitable ones of the components of the RF device 2500 may include a die (e.g., the die 2002 as described with reference to FIG. 5 or a die implementing the IC structure as described with reference to FIG. 1 or 2) including one or more planar transistors with wrap-around gates and/or one or more wrap-around S/D contacts in accordance with any of the embodiments disclosed herein. Any of the components of the RF device 2500 may include an IC device (e.g., the IC structure of FIGS. 1-2) and/or an IC package 2200 as described with reference to FIG. 6. Any of the components of the RF device 2500 may include an IC device assembly 2300 as described with reference to FIG. 7. In some embodiments, the RF device 2500 may be included within any components of the computing device 2400 as described with reference to FIG. 8, or may be coupled to any of the components of the computing device 2400, e.g., be coupled to the memory 2404 and/or to the processing device 2402 of the computing device 2400. In still other embodiments, the RF device 2500 may further include any of the components described with reference to FIG. 8, such as, but not limited to, the battery/power circuit 2414, the memory 2404, and various input and output devices as shown in FIG. 8.

In general, the RF device 2500 may be any device or system that may support wireless transmission and/or reception of signals in the form of electromagnetic waves in the RF range of approximately 3 kiloHertz (kHz) to 300 gigaHertz (GHz). In some embodiments, the RF device 2500 may be used for wireless communications, e.g., in a BS or a UE device of any suitable cellular wireless communications technology, such as GSM, WCDMA, or LTE. In a further example, the RF device 2500 may be used as, or in, e.g., a BS or a UE device of a mm-wave wireless technology such as fifth generation (5G) wireless (i.e., high frequency/short wavelength spectrum, e.g., with frequencies in the range between about 20 and 60 GHz, corresponding to wavelengths in the range between about 5 and 15 millimeters). In yet another example, the RF device 2500 may be used for wireless communications using Wi-Fi technology (e.g., a frequency band of 2.4 GHz, corresponding to a wavelength of about 12 cm, or a frequency band of 5.8 GHz, spectrum, corresponding to a wavelength of about 5 cm), e.g., in a Wi-Fi-enabled device such as a desktop, a laptop, a video game console, a smart phone, a tablet, a smart TV, a digital audio player, a car, a printer, etc. In some implementations, a Wi-Fi-enabled device may, e.g., be a node in a smart system configured to communicate data with other nodes, e.g., a smart sensor. Still in another example, the RF device 2500 may be used for wireless communications using Bluetooth technology (e.g., a frequency band from about 2.4 to about 2.485 GHz, corresponding to a wavelength of about 12 cm). In other embodiments, the RF device 2500 may be used for transmitting and/or receiving RF signals for purposes other than communication, e.g., in an automotive radar system, or in medical applications such as magneto-resonance imaging (MRI).

In various embodiments, the RF device 2500 may be included in frequency-domain duplex (FDD) or time-domain duplex (TDD) variants of frequency allocations that may be used in a cellular network. In an FDD system, the uplink (i.e., RF signals transmitted from the UE devices to a BS) and the downlink (i.e., RF signals transmitted from the BS to the US devices) may use separate frequency bands at the same time. In a TDD system, the uplink and the downlink may use the same frequencies but at different times.

A number of components are illustrated in FIG. 9 as included in the RF device 2500, but any one or more of these components may be omitted or duplicated, as suitable for the application. For example, in some embodiments, the RF device 2500 may be an RF device supporting both of wireless transmission and reception of RF signals (e.g., an RF transceiver), in which case it may include both the components of what is referred to herein as a transmit (TX) path and the components of what is referred to herein as a receive (RX) path. However, in other embodiments, the RF device 2500 may be an RF device supporting only wireless reception (e.g., an RF receiver), in which case it may include the components of the RX path, but not the components of the TX path; or the RF device 2500 may be an RF device supporting only wireless transmission (e.g., an RF transmitter), in which case it may include the components of the TX path, but not the components of the RX path.

In some embodiments, some or all of the components included in the RF device 2500 may be attached to one or more motherboards. In some embodiments, some or all of these components are fabricated on a single die, e.g., on a single SoC die.

Additionally, in various embodiments, the RF device 2500 may not include one or more of the components illustrated in FIG. 9, but the RF device 2500 may include interface circuitry for coupling to the one or more components. For example, the RF device 2500 may not include an antenna 2502, but may include antenna interface circuitry (e.g., a matching circuitry, a connector and driver circuitry) to which an antenna 2502 may be coupled. In another set of examples, the RF device 2500 may not include a digital processing unit 2508 or a local oscillator 2506, but may include device interface circuitry (e.g., connectors and supporting circuitry) to which a digital processing unit 2508 or a local oscillator 2506 may be coupled.

As shown in FIG. 9, the RF device 2500 may include an antenna 2502, a duplexer 2504, a local oscillator 2506, a digital processing unit 2508. As also shown in FIG. 9, the RF device 2500 may include an RX path which may include an RX path amplifier 2512, an RX path pre-mix filter 2514, a RX path mixer 2516, an RX path post-mix filter 2518, and an analog-to-digital converter (ADC) 2520. As further shown in FIG. 9, the RF device 2500 may include a TX path which may include a TX path amplifier 2522, a TX path post-mix filter 2524, a TX path mixer 2526, a TX path pre-mix filter 2528, and a digital-to-analog converter (DAC) 2530. Still further, the RF device 2500 may further include an impedance tuner 2532 and an RF switch 2534. In various embodiments, the RF device 2500 may include multiple instances of any of the components shown in FIG. 9. In some embodiments, the RX path amplifier 2512, the TX path amplifier 2522, the duplexer 2504, and the RF switch 2534 may be considered to form, or be a part of, an RF FE of the RF device 2500. In some embodiments, the RX path mixer 2516 and the TX path mixer 2526 (possibly with their associated pre-mix and post-mix filters shown in FIG. 9) may be considered to form, or be a part of, an RF transceiver of the RF device 2500 (or of an RF receiver or an RF transmitter if only RX path or TX path components, respectively, are included in the RF device 2500). Although not specifically shown in FIG. 9, the RF device 2500 may further include one or more control logic elements/circuits for an RF device (e.g., in an RF FR control interface), e.g., to enhance control of complex RF system environment, support implementation of envelope tracking techniques, reduce dissipated power, etc. Various IC structures as described herein may be particularly advantageous for realizing at least portions of such control logic elements/circuits.

The antenna 2502 may be configured to wirelessly transmit and/or receive RF signals in accordance with any wireless standards or protocols, e.g., Wi-Fi, LTE, or GSM, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. If the RF device 2500 is an FDD transceiver, the antenna 2502 may be configured for concurrent reception and transmission of communication signals in separate (i.e., non-overlapping and non-continuous) bands of frequencies, e.g. in bands having a separation of, e.g., 20 MHz from one another. If the RF device 2500 is a TDD transceiver, the antenna 2502 may be configured for sequential reception and transmission of communication signals in bands of frequencies which may be the same, or overlapping for TX and RX paths. In some embodiments, the RF device 2500 may be a multi-band RF device, in which case the antenna 2502 may be configured for concurrent reception of signals having multiple RF components in separate frequency bands and/or configured for concurrent transmission of signals having multiple RF components in separate frequency bands. In such embodiments, the antenna 2502 may be a single wide-band antenna or a plurality of band-specific antennas (i.e., a plurality of antennas each configured to receive and/or transmit signals in a specific band of frequencies). In various embodiments, the antenna 2502 may include a plurality of antenna elements, e.g., a plurality of antenna elements forming a phased antenna array (i.e., a communication system or an array of antennas that may use a plurality of antenna elements and phase shifting to transmit and receive RF signals). Compared to a single-antenna system, a phased antenna array may offer advantages such as increased gain, ability of directional steering, and simultaneous communication. In some embodiments, the RF device 2500 may include more than one antenna 2502 to implement antenna diversity. In some such embodiments, the RF switch 2534 may be deployed to switch between different antennas.

An output of the antenna 2502 may be coupled to the input of the duplexer 2504. The duplexer 2504 may be any suitable component configured for filtering multiple signals to allow for bidirectional communication over a single path between the duplexer 2504 and the antenna 2502. The duplexer 2504 may be configured for providing RX signals to the RX path of the RF device 2500 and for receiving TX signals from the TX path of the RF device 2500.

The RF device 2500 may include one or more local oscillators 2506, configured to provide local oscillator signals which may be used for downconversion of the RF signals received by the antenna 2502 and/or upconversion of the signals to be transmitted by the antenna 2502.

The RF device 2500 may include the digital processing unit 2508, which may include one or more processing devices. In some embodiments, the digital processing unit 2508 may be implemented as the processing device 2402 shown in FIG. 8, descriptions of which are provided above (when used as the digital processing unit 2508, the processing device 2402 may, but does not have to, implement any of the IC structures as described herein, e.g., IC structures having one or more planar transistors with wrap-around gates and/or one or more wrap-around S/D contacts in accordance with any of the embodiments disclosed herein). The digital processing unit 2508 may be configured to perform various functions related to digital processing of the RX and/or TX signals. Examples of such functions include, but are not limited to, decimation/downsampling, error correction, digital downconversion or upconversion, DC offset cancellation, automatic gain control, etc. Although not shown in FIG. 9, in some embodiments, the RF device 2500 may further include a memory device, e.g., the memory device 2404 as described with reference to FIG. 8, configured to cooperate with the digital processing unit 2508. When used within, or coupled to, the RF device 2500, the memory device 2404 may, but does not have to, implement any of the IC structures as described herein, e.g., IC structures having one or more planar transistors with wrap-around gates and/or one or more wrap-around S/D contacts in accordance with any of the embodiments disclosed herein.

Turning to the details of the RX path that may be included in the RF device 2500, the RX path amplifier 2512 may include a low-noise amplifier (LNA). An input of the RX path amplifier 2512 may be coupled to an antenna port (not shown) of the antenna 2502, e.g., via the duplexer 2504. The RX path amplifier 2512 may amplify the RF signals received by the antenna 2502.

An output of the RX path amplifier 2512 may be coupled to an input of the RX path pre-mix filter 2514, which may be a harmonic or band-pass (e.g., low-pass) filter, configured to filter received RF signals that have been amplified by the RX path amplifier 2512.

An output of the RX path pre-mix filter 2514 may be coupled to an input of the RX path mixer 2516, also referred to as a downconverter. The RX path mixer 2516 may include two inputs and one output. A first input may be configured to receive the RX signals, which may be current signals, indicative of the signals received by the antenna 2502 (e.g., the first input may receive the output of the RX path pre-mix filter 2514). A second input may be configured to receive local oscillator signals from one of the local oscillators 2506. The RX path mixer 2516 may then mix the signals received at its two inputs to generate a downconverted RX signal, provided at an output of the RX path mixer 2516. As used herein, downconversion refers to a process of mixing a received RF signal with a local oscillator signal to generate a signal of a lower frequency. In particular, the downconverting RX path mixer 2516 may be configured to generate the sum and/or the difference frequency at the output port when two input frequencies are provided at the two input ports. In some embodiments, the RF device 2500 may implement a direct-conversion receiver (DCR), also known as homodyne, synchrodyne, or zero-IF receiver, in which case the RX path mixer 2516 may be configured to demodulate the incoming radio signals using local oscillator signals whose frequency is identical to, or very close to the carrier frequency of the radio signal. In other embodiments, the RF device 2500 may make use of downconversion to an intermediate frequency (IF). IFs may be used in superheterodyne radio receivers, in which a received RF signal is shifted to an IF, before the final detection of the information in the received signal is done. Conversion to an IF may be useful for several reasons. For example, when several stages of filters are used, they can all be set to a fixed frequency, which makes them easier to build and to tune. In some embodiments, the RX path mixer 2516 may include several such stages of IF conversion.

Although a single RX path mixer 2516 is shown in the RX path of FIG. 9, in some embodiments, the RX path mixer 2516 may be implemented as a quadrature downconverter, in which case it would include a first RX path mixer and a second RX path mixer. The first RX path mixer may be configured for performing downconversion to generate an in-phase (I) downconverted RX signal by mixing the RX signal received by the antenna 2502 and an in-phase component of the local oscillator signal provided by the local oscillator 2506. The second RX path mixer may be configured for performing downconversion to generate a quadrature (Q) downconverted RX signal by mixing the RX signal received by the antenna 2502 and a quadrature component of the local oscillator signal provided by the local oscillator 2506 (the quadrature component is a component that is offset, in phase, from the in-phase component of the local oscillator signal by 90 degrees). The output of the first RX path mixer may be provided to a I-signal path, and the output of the second RX path mixer may be provided to a Q-signal path, which may be substantially 90 degrees out of phase with the I-signal path.

The output of the RX path mixer 2516 may, optionally, be coupled to the RX path post-mix filter 2518, which may be low-pass filters. In case the RX path mixer 2516 is a quadrature mixer that implements the first and second mixers as described above, the in-phase and quadrature components provided at the outputs of the first and second mixers respectively may be coupled to respective individual first and second RX path post-mix filters included in the filter 2518.

The ADC 2520 may be configured to convert the mixed RX signals from the RX path mixer 2516 from analog to digital domain. The ADC 2520 may be a quadrature ADC that, similar to the RX path quadrature mixer 2516, may include two ADCs, configured to digitize the downconverted RX path signals separated in in-phase and quadrature components. The output of the ADC 2520 may be provided to the digital processing unit 2508, configured to perform various functions related to digital processing of the RX signals so that information encoded in the RX signals can be extracted.

Turning to the details of the TX path that may be included in the RF device 2500, the digital signal to later be transmitted (TX signal) by the antenna 2502 may be provided, from the digital processing unit 2508, to the DAC 2530. Similar to the ADC 2520, the DAC 2530 may include two DACs, configured to convert, respectively, digital I- and Q-path TX signal components to analog form.

Optionally, the output of the DAC 2530 may be coupled to the TX path pre-mix filter 2528, which may be a band-pass (e.g., low-pass) filter (or a pair of band-pass, e.g., low-pass, filters, in case of quadrature processing) configured to filter out, from the analog TX signals output by the DAC 2530, the signal components outside of the desired band. The digital TX signals may then be provided to the TX path mixer 2526, which may also be referred to as an upconverter. Similar to the RX path mixer 2516, the TX path mixer 2526 may include a pair of TX path mixers, for in-phase and quadrature component mixing. Similar to the first and second RX path mixers that may be included in the RX path, each of the TX path mixers of the TX path mixer 2526 may include two inputs and one output. A first input may receive the TX signal components, converted to the analog form by the respective DAC 2530, which are to be upconverted to generate RF signals to be transmitted. The first TX path mixer may generate an in-phase (I) upconverted signal by mixing the TX signal component converted to analog form by the DAC 2530 with the in-phase component of the TX path local oscillator signal provided from the local oscillator 2506 (in various embodiments, the local oscillator 2506 may include a plurality of different local oscillators, or be configured to provide different local oscillator frequencies for the mixer 2516 in the RX path and the mixer 2526 in the TX path). The second TX path mixer may generate a quadrature phase (Q) upconverted signal by mixing the TX signal component converted to analog form by the DAC 2530 with the quadrature component of the TX path local oscillator signal. The output of the second TX path mixer may be added to the output of the first TX path mixer to create a real RF signal. A second input of each of the TX path mixers may be coupled the local oscillator 2506.

Optionally, the RF device 2500 may include the TX path post-mix filter 2524, configured to filter the output of the TX path mixer 2526.

The TX path amplifier 2522 may be a power amplifier (PA), configured to amplify the upconverted RF signal before providing it to the antenna 2502 for transmission.

In various embodiments, any of the RX path pre-mix filter 2514, the RX path post-mix filter 2518, the TX post-mix filter 2524, and the TX pre-mix filter 2528 may be implemented as RF filters. In some embodiments, each of such RF filters may include one or more, typically a plurality of, resonators (e.g., film bulk acoustic resonators (FBARs), Lamb wave resonators, and/or contour-wave resonators), arranged, e.g., in a ladder configuration. An individual resonator of an RF filter may include a layer of a piezoelectric material such as aluminum nitride (AlN), enclosed between a bottom electrode and a top electrode, with a cavity provided around a portion of each electrode in order to allow a portion of the piezoelectric material to vibrate during operation of the filter. In some embodiments, an RF filter may be implemented as a plurality of RF filters, or a filter bank. A filter bank may include a plurality of RF resonators which may be coupled to a switch, e. g., the RF switch 2534, configured to selectively switch any one of the plurality of RF resonators on and off (i.e., activate any one of the plurality of RF resonators), in order to achieve desired filtering characteristics of the filter bank (i.e., in order to program the filter bank). For example, such a filter bank may be used to switch between different RF frequency ranges when the RF device 2500 is, or is included in, a BS or in a UE device. In another example, such a filter bank may be programmable to suppress TX leakage on the different duplex distances.

The impedance tuner 2532 may include any suitable circuitry, configured to match the input and output impedances of the different RF circuitries to minimize signal losses in the RF device 2500. For example, the impedance tuner 2532 may include an antenna impedance tuner. Being able to tune the impedance of the antenna 2502 may be particularly advantageous because antenna's impedance is a function of the environment that the RF device 2500 is in, e.g. antenna's impedance changes depending on, e.g., if the antenna is held in a hand, placed on a car roof, etc.

As described above, the RF switch 2534 may be used to selectively switch between a plurality of instances of any one of the components shown in FIG. 9, in order to achieve desired behavior and characteristics of the RF device 2500. For example, in some embodiments, an RF switch may be used to switch between different antennas 2502. In other embodiments, an RF switch may be used to switch between a plurality of RF resonators (e.g., by selectively switching RF resonators on and off) of any of the filters included in the RF device 2500.

In various embodiments, one or more of the III-N transistors as described herein may be particularly advantageous when used in any of the duplexer 2504, RX path amplifier 2512, RX path pre-mix filter 2514, RX path post-mix filter 2518, TX path amplifier 2522, TX path pre-mix filter 2528, TX path post-mix filter 2524, impedance tuner 2532, and/or RF switch 2534.

The RF device 2500 provides a simplified version and, in further embodiments, other components not specifically shown in FIG. 9 may be included. For example, the RX path of the RF device 2500 may include a current-to-voltage amplifier between the RX path mixer 2516 and the ADC 2520, which may be configured to amplify and convert the downconverted signals to voltage signals. In another example, the RX path of the RF device 2500 may include a balun transformer for generating balanced signals. In yet another example, the RF device 2500 may further include a clock generator, which may, e.g., include a suitable phase-locked loop (PLL), configured to receive a reference clock signal and use it to generate a different clock signal which may then be used for timing the operation of the ADC 2520, the DAC 2530, and/or which may also be used by the local oscillator 2506 to generate the local oscillator signals to be used in the RX path or the TX path.

SELECT EXAMPLES

The following paragraphs provide various examples of the embodiments disclosed herein.

Example 1 provides an IC structure that includes a support structure, (e.g., a substrate, a die, or a chip) and a planar III-N transistor. The transistor includes a channel stack provided over the support structure, the channel stack including a III-N semiconductor material provided over the support structure, and a polarization material provided over the III-N semiconductor material, a first and a second source/drain (S/D) regions provided in the channel stack, and a gate stack provided over a portion of the channel stack between the first and the second S/D regions, where the gate stack at least partially wraps around an upper portion of the channel stack.

Example 2 provides the IC structure according to example 1, where the gate stack wrapping around the upper portion of the channel stack includes the gate stack being provided over an upper face (e.g., the face of the channel stack being farthest away from the support structure) of the channel stack and extending to a depth between about 2 and 100 nanometers, including all values and ranges therein, e.g., between about 4 and 50 nanometers, or between about 5 and 30 nanometers, along at least one sidewall (preferably along both sidewalls) of the channel stack.

Example 3 provides the IC structure according to example 2, where the gate stack includes a gate dielectric material wrapping around the upper portion of the channel stack, and a gate electrode material wrapping around the gate dielectric material.

Example 4 provides the IC structure according to example 3, where a portion of the gate dielectric material is in contact with the III-N semiconductor material at the at least one sidewall of the channel stack.

Example 5 provides the IC structure according to any one of the preceding examples, where each of the first and the second S/D regions extends into the channel stack to a depth between about 8 and 200 nanometers, including all values and ranges therein, e.g., between about 10 and 150 nanometers, or between about 10 and 80 nanometers.

Example 6 provides the IC structure according to any one of the preceding examples, where a width of the channel stack in a direction perpendicular to a gate length is between about 20 nanometers and 1 millimeter, including all values and ranges therein, e.g., between about 50 nanometers and 500 micrometers, or between about 100 nanometers and 50 micrometers.

Example 7 provides the IC structure according to any one of the preceding examples, where the polarization material includes a material having stronger piezo-polarization behavior/properties than the III-N semiconductor material and configured to induce a tensile stress in the III-N semiconductor material.

Example 8 provides the IC structure according to example 7, where the polarization material includes aluminum, indium, gallium, and nitrogen (e.g., Al_(x)In_(y)Ga_(z)N).

Example 9 provides the IC structure according to any one of the preceding examples, where a thickness of the polarization material between the gate stack and the III-N semiconductor material is between about 0.1 and 50 nanometers, e.g., between about 1 and 20 nanometers, or between about 1 and 10 nanometers.

Example 10 provides the IC structure according to any one of the preceding examples, where the III-N semiconductor material includes nitrogen and one or more of gallium and aluminum (e.g., GaN, AlN, or AlGaN).

Example 11 provides the IC structure according to any one of the preceding examples, where a thickness of the III-N semiconductor material is between about 5 and 1000 nanometers, e.g., between about 5 and 100 nanometers, or between about 10 and 50 nanometers.

Example 12 provides the IC structure according to any one of the preceding examples, further including a buffer material between the III-N semiconductor material and the support structure, where a band gap of the buffer material is greater than a band gap of the III-N semiconductor material.

Example 13 provides the IC structure according to example 12, where the buffer material includes a material including aluminum, gallium, and nitrogen (e.g., AlGaN), or a material including aluminum and nitrogen (e.g., AlN).

Example 14 provides the IC structure according to examples 12 or 13, where a thickness of the buffer material is between about 100 and 5000 nanometers, e.g., between about 250 and 500 nanometers.

Example 15 provides the IC structure according to any one of the preceding examples, further including an S/D contact material (e.g., conductive material 118 used to implement the S/D contacts 126), at least partially wrapping around an upper portion of at least one of the first and the second S/D regions, e.g., of the first S/D region.

Example 16 provides the IC structure according to example 15, where the S/D contact material wrapping around the upper portion of the first S/D region includes the S/D contact material being provided over an upper face (e.g., the face of the S/D region being farthest away from the support structure) of the first S/D region and extending to a depth between about 2 and 150 nanometers, including all values and ranges therein, e.g., between about 4 and 75 nanometers, or between about 5 and 45 nanometers, along at least one sidewall (preferably along both sidewalls) of the channel stack.

Example 17 provides the IC structure according to example 16, where a portion of the S/D contact material is in contact with the at least one sidewall of the first S/D region.

Example 18 provides the IC structure according to any one of the preceding examples, where the planar III-N transistor is a part of an RF circuit, or the III-N transistor is a part of a power circuit.

Example 19 provides an IC package that includes an IC die and a further IC component, coupled to the IC die. The IC die includes a planar transistor with a channel stack and a gate stack. The channel stack includes one or more semiconductor materials (e.g., a III-N semiconductor material and a polarization material provided over the III-N semiconductor material). The channel stack has an upper face, and a pair of opposite sidewalls, where a distance between the pair of opposite sidewalls is between about 20 nanometers and 1 millimeter, including all values and ranges therein, e.g., between about 50 nanometers and 500 micrometers, or above about 100 nanometers (e.g., between about 100 nanometers and 50 micrometers). The gate stack includes a first portion in contact with a portion of the upper face of the channel stack, and a second portion in contact with a portion of at least one sidewall of the pair of opposite sidewalls of the channel stack.

Example 20 provides the IC package according to example 19, where the second portion of the gate stack is in contact with at least one of the one or more semiconductor materials of the channel stack (e.g., in contact with the III-N semiconductor material of the channel stack) at the at least one sidewall of the pair of opposite sidewalls of the channel stack.

Example 21 provides the IC package according to examples 19 or 20, where the first portion is continuous with the second portion (e.g., the gate stack wraps around at least one sidewall of the pair of opposite sidewalls of the channel stack).

Example 22 provides the IC package according to any one of examples 19-21, where the further IC component includes one of a package substrate, an interposer, or a further IC die.

Example 23 provides the IC package according to any one of examples 19-22, where the IC package is included in one of a switch, a power amplifier, a low-noise amplifier, a filter, a filter bank, a duplexer, an upconverter, a downconverter, or a logic circuit of an RF communications device, e.g. of an RF transceiver, and/or the IC package is included in a base station of a wireless communication system or in a UE device (e.g., a mobile device) of a wireless communication system.

In various further examples, the IC die of the IC package according to any one of the preceding examples may include the IC structure according to any one of the preceding examples, e.g., the IC structure according to any one of examples 1-18.

Example 24 provides a method of manufacturing an IC structure. The method includes forming a channel stack over a support structure, the channel stack including a III-N semiconductor material and a polarization material over the III-N semiconductor material; forming a pair of source/drain (S/D) regions in the channel stack; and providing a gate stack over a portion of the channel stack between the pair of S/D regions, where the gate stack at least partially wraps around an upper portion of the channel stack.

Example 25 provides the method according to example 24, where the gate stack wrapping around the upper portion of the channel stack includes the gate stack being provided over an upper face (e.g., the face of the channel stack being farthest away from the support structure) of the channel stack and extending to a depth between about 2 and 100 nanometers, including all values and ranges therein, e.g., between about 4 and 50 nanometers, or between about 5 and 30 nanometers, along at least one sidewall (preferably along both sidewalls) of the channel stack.

Example 26 provides the method according to example 24, where the channel stack includes an upper face and a pair of opposite sidewalls, and where providing the gate stack includes forming a recess in a dielectric material enclosing the pair of opposite sidewalls of the channel stack to expose a portion of at least one sidewall of the pair of opposite sidewalls of the channel stack, where a height of the exposed portion of the at least one sidewall of the pair of opposite sidewalls of the channel stack is between about 2 and 100 nanometers, including all values and ranges therein, e.g., between about 4 and 50 nanometers, or between about 5 and 30 nanometers, along at least one sidewall (preferably along both sidewalls) of the channel stack, depositing a gate dielectric material of the gate stack over the upper face of the channel stack and over the exposed portion of the at least one sidewall of the pair of opposite sidewalls of the channel stack, and depositing a gate electrode material of the gate stack over the gate dielectric material.

In various further examples of the method according to any one of examples 24-26, the IC structure is the IC structure according to any one of examples 1-18, and the method includes corresponding further processes to manufacture any of these IC structures.

Example 27 provides an IC structure that includes a support structure (e.g., a substrate, a die, or a chip) and a planar transistor. The transistor includes a channel stack provided over the support structure, the channel stack including one or more semiconductor materials provided over the support structure (e.g., a III-N semiconductor material and a polarization material provided over the III-N semiconductor material), a first and a second source/drain (S/D) regions provided in the channel stack, and an S/D contact material, where the S/D contact material at least partially wraps around an upper portion of at least one of the first and the second S/D regions, e.g., the first S/D region. If the S/D contact material wraps around the upper portion of both S/D regions, then it's different instances of said material (e.g., discontinuous material) wrapping around each respective S/D region.

Example 28 provides the IC structure according to example 27, where the S/D contact material wrapping around the upper portion of the first S/D region includes the S/D contact material being provided over an upper face (e.g., the face of the S/D region being farthest away from the support structure) of the first S/D region and extending to a depth between about 2 and 150 nanometers, including all values and ranges therein, e.g., between about 4 and 75 nanometers, or between about 5 and 45 nanometers, along at least one sidewall (preferably along both sidewalls) of the channel stack.

Example 29 provides the IC structure according to example 28, where a portion of the S/D contact material is in contact with the at least one sidewall of the first S/D region.

Example 30 provides an electronic device that includes a carrier substrate; and an IC die coupled to the carrier substrate, where the IC die includes the transistor arrangement according to any one of examples 1-18 or 27-29, and/or is included in the IC package according to any one of examples 19-23.

Example 31 provides the electronic device according to example 30, where the computing device is a wearable or handheld electronic device.

Example 32 provides the electronic device according to examples 30 or 31, where the electronic device further includes one or more communication chips and an antenna.

Example 33 provides the electronic device according to any one of examples 30-32, where the carrier substrate is a motherboard.

Example 34 provides the electronic device according to any one of examples 30-33, where the electronic device is an RF transceiver.

Example 35 provides the electronic device according to any one of examples 30-34, where the electronic device is one of a switch, a power amplifier, a low-noise amplifier, a filter, a filter bank, a duplexer, an upconverter, a downconverter, or a logic circuit (e.g., control logic) of an RF communications device, e.g. of an RF transceiver.

Example 36 provides the electronic device according to any one of examples 30-35, where the electronic device is included in a base station of a wireless communication system.

Example 37 provides the electronic device according to any one of examples 30-35, where the electronic device is included in a UE device (e.g., a mobile device) of a wireless communication system.

The above description of illustrated implementations of the disclosure, including what is described in the Abstract, is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. While specific implementations of, and examples for, the disclosure are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the disclosure, as those skilled in the relevant art will recognize. These modifications may be made to the disclosure in light of the above detailed description. 

1. An integrated circuit (IC) structure, comprising: a support structure; and a III-N transistor, comprising: a channel stack over the support structure, the channel stack including a III-N semiconductor material and a polarization material over the III-N semiconductor material, first and second source/drain (S/D) regions in the channel stack, and a gate stack over a portion of the channel stack between the first and the second S/D regions, wherein the gate stack at least partially wraps around an upper portion of the channel stack.
 2. The IC structure according to claim 1, wherein the gate stack wrapping around the upper portion of the channel stack includes the gate stack being over an upper face of the channel stack and extending to a depth between 2 and 100 nanometers along at least one sidewall of the channel stack.
 3. The IC structure according to claim 2, wherein the gate stack includes a gate dielectric material wrapping around the upper portion of the channel stack, and a gate electrode material wrapping around the gate dielectric material.
 4. The IC structure according to claim 3, wherein a portion of the gate dielectric material is in contact with the III-N semiconductor material at the at least one sidewall of the channel stack.
 5. The IC structure according to claim 1, wherein a dimension of the channel stack in a direction perpendicular to a gate length of the III-N transistor is between 20 nanometers and 1 millimeter.
 6. The IC structure according to claim 1, wherein the polarization material includes a material to induce a tensile stress in the III-N semiconductor material.
 7. The IC structure according to claim 1, wherein a thickness of the polarization material between the gate stack and the III-N semiconductor material is between 0.1 and 50 nanometers.
 8. The IC structure according to claim 1, further including a buffer material between the III-N semiconductor material and the support structure, wherein a band gap of the buffer material is greater than a band gap of the III-N semiconductor material.
 9. The IC structure according to claim 1, further comprising an S/D contact material, at least partially wrapping around an upper portion of the first S/D region.
 10. The IC structure according to claim 9, wherein the S/D contact material wrapping around the upper portion of the first S/D region includes the S/D contact material being over an upper face of the first S/D region and extending to a depth between 2 and 150 nanometers along at least one sidewall of the channel stack.
 11. The IC structure according to claim 10, wherein a portion of the S/D contact material is in contact with the at least one sidewall of the first S/D region.
 12. The IC structure according to claim 1, wherein the III-N transistor is a part of a radio frequency circuit or a power circuit.
 13. An integrated circuit (IC) package, comprising: an IC die comprising a planar transistor that includes: a channel stack of one or more semiconductor materials, the channel stack having an upper face and a pair of opposite sidewalls, wherein a distance between the pair of opposite sidewalls is greater than 100 nanometers, and a gate stack, where the gate stack includes: a first portion in contact with a portion of the upper face of the channel stack, and a second portion in contact with a portion of at least one sidewall of the pair of opposite sidewalls of the channel stack; and a further IC component, coupled to the IC die.
 14. The IC package according to claim 13, wherein the second portion of the gate stack is in contact with at least one of the one or more semiconductor materials of the channel stack at the at least one sidewall of the pair of opposite sidewalls of the channel stack.
 15. The IC package according to claim 13, wherein the first portion is continuous with the second portion.
 16. The IC package according to claim 13, wherein the further IC component includes one of a package substrate, an interposer, or a further IC die.
 17. The IC package according to claim 13, wherein the IC package is included in one of a switch, a power amplifier, a low-noise amplifier, a filter, a filter bank, a duplexer, an upconverter, a downconverter, or a logic circuit of an RF communications device.
 18. A method of manufacturing an integrated circuit (IC) structure, the method comprising: forming a channel stack over a support structure, the channel stack comprising a III-N semiconductor material and a polarization material over the III-N semiconductor material; forming a pair of source/drain (S/D) regions in the channel stack; and forming a gate stack over a portion of the channel stack between the pair of S/D regions, wherein the gate stack at least partially wraps around an upper portion of the channel stack.
 19. The method according to claim 18, wherein the gate stack wrapping around the upper portion of the channel stack includes the gate stack being over an upper face of the channel stack and extending to a depth between 2 and 100 nanometers along at least one sidewall of the channel stack.
 20. The method according to claim 18, wherein the channel stack includes an upper face and a pair of opposite sidewalls, and wherein providing the gate stack includes: forming a recess in a dielectric material enclosing the pair of opposite sidewalls of the channel stack to expose a portion of at least one sidewall of the pair of opposite sidewalls of the channel stack, where a height of the exposed portion of the at least one sidewall of the pair of opposite sidewalls of the channel stack is between 2 and 100 nanometers along at least one sidewall of the channel stack, depositing a gate dielectric material of the gate stack over the upper face of the channel stack and over the exposed portion of the at least one sidewall of the pair of opposite sidewalls of the channel stack, and depositing a gate electrode material of the gate stack over the gate dielectric material. 